scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog (by syntacore)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
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| scr1 | darkriscv | |
|---|---|---|
| 2 | 3 | |
| 775 | 1,882 | |
| 3.2% | 2.8% | |
| 3.0 | 6.3 | |
| 18 days ago | 10 days ago | |
| SystemVerilog | Verilog | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
scr1
Posts with mentions or reviews of scr1.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-07-04.
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Looking for a suitable open-source RISC-V for an embedded project
Would this be suitable? https://github.com/syntacore/scr1 I haven't used it, but I saw it in Riscduino project which continues to appear in Open MPWs.
- Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing scr1 and darkriscv you can also consider the following projects:
riscv-simple-sv - A simple RISC V core for teaching
biriscv - 32-bit Superscalar RISC-V CPU
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
XiangShan - Open-source high-performance RISC-V processor
friscv - RISCV CPU implementation in SystemVerilog
riscv - RISC-V CPU Core (RV32IM)
clic - RISC-V fast interrupt controller
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
Cores-VeeR-EL2 - VeeR EL2 Core