Verilog Rtl

Open-source Verilog projects categorized as Rtl

Top 4 Verilog Rtl Projects

  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Project mention: [D][P] Represent Analog Circuits as Graphs | | 2023-04-15

    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.

  • InfluxDB

    Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.

  • OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at

    Project mention: OpenROAD: Open IC Design Sythesis from Verilog | | 2023-04-24
  • boxlambda

    FPGA based microcomputer sandbox for software and RTL experimentation

    Project mention: BoxLambda DevLog: Hello Debugger! | | 2022-08-29

    BoxLambda is a Blog and an open-source project with the goal of creating a retro-style FPGA-based microcomputer. The microcomputer serves as a platform for software and RTL experimentation.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-04-24.

Verilog Rtl related posts


What are some of the best open-source Rtl projects in Verilog? This list will help you:

Project Stars
1 darkriscv 1,626
2 openlane 904
3 OpenROAD 852
4 boxlambda 23
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