Top 4 Verilog Rtl Projects
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.Project mention: [D][P] Represent Analog Circuits as Graphs | reddit.com/r/MachineLearning | 2023-04-15
I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/Project mention: OpenROAD: Open IC Design Sythesis from Verilog | news.ycombinator.com | 2023-04-24
FPGA based microcomputer sandbox for software and RTL experimentationProject mention: BoxLambda DevLog: Hello Debugger! | reddit.com/r/FPGA | 2022-08-29
BoxLambda is a Blog and an open-source project with the goal of creating a retro-style FPGA-based microcomputer. The microcomputer serves as a platform for software and RTL experimentation.
Verilog Rtl related posts
Simple skid buffer implementation
3 projects | reddit.com/r/FPGA | 10 Jan 2023
6 projects | reddit.com/r/chipdesign | 14 Dec 2022
Any recommendations for an RTL "standard library"?
9 projects | reddit.com/r/FPGA | 18 Nov 2021
Share some github FPGA projects (bonus if they include C++, Python, or other files)
15 projects | reddit.com/r/FPGA | 14 Sep 2021
What are some of the best open-source Rtl projects in Verilog? This list will help you: