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Mentions Stars Project Description
3 173 Bus bridges and other odds and ends
3 0 Q*Bert core for MiSTer [Moved to: https://github.com/MiSTer-devel/Arcade-QBert_MiSTer]
2 714 HDL libraries and projects
2 671 Verilog Ethernet components for FPGA implementation
2 375 A tiny Open POWER ISA softcore written in VHDL 2008
2 92 A Video display simulator
1 535 The USRP™ Hardware Driver Repository
1 342 SERV - The SErial RISC-V CPU
1 140 Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
1 123 Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
1 92 A second generation low-cost amateur HF software defined radio transceiver.
1 66 NeoGeo for MiSTer
1 42 Mega CD for MiSTer
1 15 A ZipCPU based demonstration of the MAX1000 FPGA board
1 12 A System on a Chip Implementation for the XuLA2-LX25 board
1 5 PID controller
1 5 Designing a 16-bit CPU made from TTL chips.
1 0
1 0 This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.
1 0 Q*Bert core for MiSTer

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