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Mentions Stars Project Description
8 30 OpenXuantie - OpenC910 Core
3 13 OpenXuantie - OpenC906 Core
2 1,789 PicoRV32 - A Size-Optimized RISC-V CPU
2 700 Open source, high performance, FPGA-based NIC
2 543 SERV - The SErial RISC-V CPU
2 1 Scooter Shooter for MiSTer
2 1 PMD85 v.2A for MISTer
1 437 OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
1 380 RISC-V CPU Core (RV32IM)
1 232 Bus bridges and other odds and ends
1 138 Example designs showing different ways to use SymbiFlow toolchains.
1 108 Everything around N64 and RGB
1 91 MIPSfpga+ allows loading programs via UART and has a switchable clock
1 76 CDBUS Protocol and the IP Core for FPGA users
1 65 Gameboy for MiSTer
1 25 HDMI interface for GameBoy DMG
1 13 Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
1 7 Verilog dbus (TI transfer bus) implementation and bridge to UART. High-performance link with TI calculators such as TI-89.
1 3 SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
1 3 PID controller on an FPGA with custom RS232 addressing protocol.

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