62
69
103
| Mentions | Stars | Project | Description |
|---|---|---|---|
| 3 | 173 | Bus bridges and other odds and ends | |
| 3 | 0 | Q*Bert core for MiSTer [Moved to: https://github.com/MiSTer-devel/Arcade-QBert_MiSTer] | |
| 2 | 714 | HDL libraries and projects | |
| 2 | 671 | Verilog Ethernet components for FPGA implementation | |
| 2 | 375 | A tiny Open POWER ISA softcore written in VHDL 2008 | |
| 2 | 92 | A Video display simulator | |
| 1 | 535 | The USRP™ Hardware Driver Repository | |
| 1 | 342 | SERV - The SErial RISC-V CPU | |
| 1 | 140 | Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker) | |
| 1 | 123 | Tool to generate register RTL, models, and docs using SystemRDL or JSpec input | |
| 1 | 92 | A second generation low-cost amateur HF software defined radio transceiver. | |
| 1 | 66 | NeoGeo for MiSTer | |
| 1 | 42 | Mega CD for MiSTer | |
| 1 | 15 | A ZipCPU based demonstration of the MAX1000 FPGA board | |
| 1 | 12 | A System on a Chip Implementation for the XuLA2-LX25 board | |
| 1 | 5 | PID controller | |
| 1 | 5 | Designing a 16-bit CPU made from TTL chips. | |
| 1 | 0 | ||
| 1 | 0 | This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz. | |
| 1 | 0 | Q*Bert core for MiSTer |
Popular Verilog Topics
Latest Mentions
Latest mentioned Verilog repos
| Stars | Project |
|---|---|
| 2 | Bluster |
| 15 | MemTest_MiSTer |
| 714 | hdl |
| 0 | Bandai2003 |
| 75 | Genesis_MiSTer |
| 71 | cpus-caddr |
| 8 | ha1588 |
| 12 | FPGA_NTP_SERVER |
| 173 | wb2axip |
| 114 | iceGDROM |
| 3 | vga_lcd |
| 1 | openvga |
| 459 | open-fpga-verilog-tutorial |
| 105 | a2o |
| 55 | sd2snes |
| 535 | uhd |
| 671 | verilog-ethernet |
| 241 | verilog-pcie |
| 92 | Hermes-Lite2 |
| 5 | scamp-cpu |
Latest Discoveries
Latest discovered Verilog repos
| Stars | Project |
|---|---|
| 2 | Bluster |
| 0 | Bandai2003 |
| 75 | Genesis_MiSTer |
| 12 | FPGA_NTP_SERVER |
| 8 | ha1588 |
| 114 | iceGDROM |
| 3 | vga_lcd |
| 1 | openvga |
| 459 | open-fpga-verilog-tutorial |
| 105 | a2o |
| 535 | uhd |
| 714 | hdl |
| 92 | Hermes-Lite2 |
| 5 | scamp-cpu |
| 0 | Arcade-QBert_MiSTer |
| 140 | ice40-playground |
| 0 | SDRAM_Controller_Verilog |
| 0 | QBert_MiSTer |
| 342 | serv |
| 671 | verilog-ethernet |