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Stars Project Description
4 54
3 1,302 Verilog Ethernet components for FPGA implementation
3 323 Bus bridges and other odds and ends
2 2,209 PicoRV32 - A Size-Optimized RISC-V CPU
2 994 Open source FPGA-based NIC and platform for in-network compute
2 299 VRoom! RISC-V CPU
2 196 OpenXuantie - OpenC906 Core
2 4 adi's adrv9371 example integration with DVB-S2 IP
2 2 alpha denshi 68k
1 212 Repository for the SCALE-MAMBA MPC system
1 97 A collection of demonstration digital filters
1 67 Verilog Implementation of an ARM LEGv8 CPU
1 65 Implemetation of pipelined ARM7TDMI processor in Verilog
1 64 该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求,在FPGA上搭建Cortex-M3软核、图像协处理器,并通过OV5640摄像头采集车牌图像,实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核,依据AHB-Lite总线协议,将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端,设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据(对应20张车牌)存储在RAM中,输出至AHB总线,由Cortex-M3调用并显示识别结果。
1 59 A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
1 45 This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
1 29 Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.
1 6 LimeSDR Mini v2 gateware project
1 2 FPGA PDP-11 for the PiDP-11 panel
1 1 Here you can find the RTL for a SPI+Register bank controller which can be used to test stand-alone Analog/Digital IP

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