Simple skid buffer implementation

• SpinalHDL

  8 1,613 9.7 Scala

  Scala based HDL

  

  I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.

• InfluxDB

  www.influxdata.com featured

  Purpose built for real-time analytics at any scale. InfluxDB Platform is powered by columnar analytics, optimized for cost-efficient storage, and built with open data standards.

  

• wb2axip

  51 469 3.1 Verilog

  Bus bridges and other odds and ends

  I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)

• TCB

  1 1 8.2 SystemVerilog

  Tightly Coupled Bus, low complexity, high performance system bus.

  I am working on a simple system bus specification TCB, so I spent some time reading your article. I hope to write the required formal rules someday, but a full input/output/state transition table would also be useful for readers. The implementation correctness can be shown by arguing all rows in a logic table provide the correct behavior. This is not very useful for verification automation, but can be easier to understand for readers with basic logic design education.

Suggest a related project