Top 23 Verilog Verilog Projects

darkriscv

3 2,091 8.4 Verilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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OpenROAD

8 1,529 10.0 Verilog

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Project mention: DARPA Brings Next-Gen US Microelectronics Manufacturing Closer to Reality | news.ycombinator.com | 2024-07-26

DARPA ERI also facilitates chiplet interconnect standards and open FPGA toolchains, https://theopenroadproject.org & https://news.ycombinator.com/item?id=30538809
hdl

5 1,495 9.5 Verilog

HDL libraries and projects
serv

22 1,391 7.6 Verilog

SERV - The SErial RISC-V CPU

Project mention: Flexible RISC-V Processor: Could Cost Less Than a Dollar | news.ycombinator.com | 2024-09-29

For those who don't know SERV is a serial RISC-V architecture - really small, fits in a Tiny Tapeout tile
https://github.com/olofk/serv
zipcpu

13 1,281 7.3 Verilog

A small, light weight, RISC CPU soft core
riscv

2 1,197 1.8 Verilog

RISC-V CPU Core (RV32IM)
biriscv

6 838 0.0 Verilog

32-bit Superscalar RISC-V CPU
USB_C_Industrial_Camera_FPGA_USB3

3 803 5.4 Verilog

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Project mention: Barcelona Supercomputing Center presents Sargantana: new open-source RISC-V chip | news.ycombinator.com | 2023-12-14

>Likely you couldn't even go back and make a fab that makes large volumes of 60nm-90nm node sizes at all, for any amount of money, because the equipment to do this (new) hasn't been made in 2 decades and no company is willing to invest the money to make new crappy old equipment.
I believe your argument assumes that there is a fixed cost to produce even 180nm or 350nm ICs that hasnt changed since the first one was produced.
We still need 300 years for a 300 year old tree, but 25 year old technology might now be relatively easy to build if we start from scratch.
What was high tech then might be relatively easy to solve now. One example might be https://github.com/circuitvalley/USB_C_Industrial_Camera_FPG... being open source instead of a multi year, multi million dollar project.
apio

3 794 9.6 Verilog

:seedling: Open source ecosystem for open FPGA boards
open-fpga-verilog-tutorial

3 759 0.0 Verilog

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
OpenTimer

1 545 0.0 Verilog

A High-performance Timing Analysis Tool for VLSI Systems
OpenROAD-flow-scripts

1 320 9.9 Verilog

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Nuked-MD-FPGA

6 298 7.7 Verilog

Mega Drive/Genesis core written in Verilog

Project mention: FPGAs and the Renaissance of Retro Hardware | news.ycombinator.com | 2023-11-27

The reality is that the vast majority of these FPGA-based clones don't actually perfectly emulate the logic. They're using the same reverse engineering techniques the traditional emulator developers used and sometimes even the same community documentation. The results are often quite good, but they're making a new implementation that matches the observed behavior of the original system to the best of their abilities.
Now there are some exceptions. Nuked MD FPGA[0] is a recent example of an FPGA recreation that is a fairly direct translation of the original logic using silicon die analysis. In this case, the logic is basically identical, but as you guessed the physical layout is different. Generally speaking, you write FPGA "gateware" in a language like Verilog or VHDL. These don't intrinsically have any information about the physical layout of the logic which is handled by the toolchain instead. As wmf says, this is generally not a problem most of the time. For synchronous logic, either the total propagation delay is small enough for a single cycle or it isn't. The toolchain will estimate this delay and report whether you met timing or not for the configured clockspeed.
Not everything you can do in silicon translates well to FPGAs (both clock edges is also generally not well supported for instance), but for the most part these things are easy enough to work around.
[0] https://github.com/nukeykt/Nuked-MD-FPGA
wbuart32

4 276 4.6 Verilog

A simple, basic, formally verified UART controller
f4pga-examples

1 263 4.3 Verilog

Example designs showing different ways to use F4PGA toolchains.
FPGA-SDcard-Reader

1 245 3.8 Verilog

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
sdspi

4 193 9.0 Verilog

SD-Card controller, using either SPI, SDIO, or eMMC interfaces
vgasim

11 152 1.2 Verilog

A Video display simulator
cpu11

2 153 6.4 Verilog

Revengineered ancient PDP-11 CPUs, originals and clones
icestation-32

1 151 0.0 Verilog

Compact FPGA game console

Project mention: The 8-Bit Era: Eight Iconic Processor Designs – By Babbage | news.ycombinator.com | 2023-12-04

> Or maybe there's a RV32I community for writing retro style games, with some simple graphics support?
Wow, https://github.com/dan-rodrigues/icestation-32 looks cool. Sorry for the comment spam. :)
dspfilters

2 139 3.5 Verilog

A collection of demonstration digital filters
apple-one

2 134 4.5 Verilog

An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
Haasoscope

1 112 4.9 Verilog

Docs, design, firmware, and software for the Haasoscope

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Verilog Verilog discussion

Verilog Verilog related posts

Flexible RISC-V Processor: Could Cost Less Than a Dollar

1 project | news.ycombinator.com | 29 Sep 2024
SERV – The SErial RISC-V CPU

1 project | news.ycombinator.com | 8 Aug 2024
DARPA Brings Next-Gen US Microelectronics Manufacturing Closer to Reality

1 project | news.ycombinator.com | 26 Jul 2024
RISC-V support in Android just got a big setback

4 projects | news.ycombinator.com | 30 Apr 2024
FuryGpu – Custom PCIe FPGA GPU

16 projects | news.ycombinator.com | 27 Mar 2024
Importance of Open-Source EDA Tools for Academia

2 projects | news.ycombinator.com | 11 Mar 2024
Barcelona Supercomputing Center presents Sargantana: new open-source RISC-V chip

3 projects | news.ycombinator.com | 14 Dec 2023
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www.saashub.com | 5 Oct 2024

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Index

What are some of the best open-source Verilog projects in Verilog? This list will help you:

	Project	Stars
1	darkriscv	2,091
2	OpenROAD	1,529
3	hdl	1,495
4	serv	1,391
5	zipcpu	1,281
6	riscv	1,197
7	biriscv	838
8	USB_C_Industrial_Camera_FPGA_USB3	803
9	apio	794
10	open-fpga-verilog-tutorial	759
11	OpenTimer	545
12	OpenROAD-flow-scripts	320
13	Nuked-MD-FPGA	298
14	wbuart32	276
15	f4pga-examples	263
16	FPGA-SDcard-Reader	245
17	sdspi	193
18	vgasim	152
19	cpu11	153
20	icestation-32	151
21	dspfilters	139
22	apple-one	134
23	Haasoscope	112

Verilog Verilog

Top 23 Verilog Verilog Projects

Verilog Verilog discussion

Verilog Verilog related posts

Flexible RISC-V Processor: Could Cost Less Than a Dollar

SERV – The SErial RISC-V CPU

DARPA Brings Next-Gen US Microelectronics Manufacturing Closer to Reality

RISC-V support in Android just got a big setback

FuryGpu – Custom PCIe FPGA GPU

Importance of Open-Source EDA Tools for Academia

Barcelona Supercomputing Center presents Sargantana: new open-source RISC-V chip

Index

Did you konow that Verilog is the 47th most popular programming language based on number of metions?

Did you konow that Verilog is
the 47th most popular programming language
based on number of metions?