Top 23 Verilog Verilog Projects

• darkriscv

  3 1,873 6.8 Verilog

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  

• hdl

  5 1,374 9.0 Verilog

  HDL libraries and projects

  

• WorkOS

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• OpenROAD

  7 1,322 10.0 Verilog

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  

  Project mention: Importance of Open-Source EDA Tools for Academia | news.ycombinator.com | 2024-03-11

  > [1]: https://theopenroadproject.org/

  All it takes to check your point is to scroll down to the end and follow the link at the bottom of the page to the FOSSI foundation, who hosted this open letter, to realize that they have also developed some widely used EDA tools. Here's a link on case you have missed it

  https://fossi-foundation.org/our-work/projects

• serv

  19 1,234 7.7 Verilog

  SERV - The SErial RISC-V CPU

  Project mention: SERV – The SErial RISC-V CPU | news.ycombinator.com | 2023-12-10

• zipcpu

  13 1,188 6.3 Verilog

  A small, light weight, RISC CPU soft core

• riscv

  2 1,040 1.8 Verilog

  RISC-V CPU Core (RV32IM)

  Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

  I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

• apio

  3 750 9.7 Verilog

  :seedling: Open source ecosystem for open FPGA boards

  

  Project mention: Looking for help getting started with TinyFPGA | /r/FPGA | 2023-07-08

  apio is a python package you drive from the command line. I didn't know somebody had done an integration with Atom. I've installed and used apio on my phone. I wouldn't really recommend doing that, but it shows what's possible.

• InfluxDB

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• biriscv

  6 749 0.0 Verilog

  32-bit Superscalar RISC-V CPU

  Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• open-fpga-verilog-tutorial

  3 743 0.0 Verilog

  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

• USB_C_Industrial_Camera_FPGA_USB3

  3 701 5.4 Verilog

  Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

  Project mention: Barcelona Supercomputing Center presents Sargantana: new open-source RISC-V chip | news.ycombinator.com | 2023-12-14

  >Likely you couldn't even go back and make a fab that makes large volumes of 60nm-90nm node sizes at all, for any amount of money, because the equipment to do this (new) hasn't been made in 2 decades and no company is willing to invest the money to make new crappy old equipment.

  I believe your argument assumes that there is a fixed cost to produce even 180nm or 350nm ICs that hasnt changed since the first one was produced.

  We still need 300 years for a 300 year old tree, but 25 year old technology might now be relatively easy to build if we start from scratch.

  What was high tech then might be relatively easy to solve now. One example might be https://github.com/circuitvalley/USB_C_Industrial_Camera_FPG... being open source instead of a multi year, multi million dollar project.

• OpenTimer

  1 508 0.0 Verilog

  A High-performance Timing Analysis Tool for VLSI Systems

  

• Nuked-MD-FPGA

  6 282 9.1 Verilog

  Mega Drive/Genesis core written in Verilog

  Project mention: FPGAs and the Renaissance of Retro Hardware | news.ycombinator.com | 2023-11-27

  The reality is that the vast majority of these FPGA-based clones don't actually perfectly emulate the logic. They're using the same reverse engineering techniques the traditional emulator developers used and sometimes even the same community documentation. The results are often quite good, but they're making a new implementation that matches the observed behavior of the original system to the best of their abilities.

  Now there are some exceptions. Nuked MD FPGA[0] is a recent example of an FPGA recreation that is a fairly direct translation of the original logic using silicon die analysis. In this case, the logic is basically identical, but as you guessed the physical layout is different. Generally speaking, you write FPGA "gateware" in a language like Verilog or VHDL. These don't intrinsically have any information about the physical layout of the logic which is handled by the toolchain instead. As wmf says, this is generally not a problem most of the time. For synchronous logic, either the total propagation delay is small enough for a single cycle or it isn't. The toolchain will estimate this delay and report whether you met timing or not for the configured clockspeed.

  Not everything you can do in silicon translates well to FPGAs (both clock edges is also generally not well supported for instance), but for the most part these things are easy enough to work around.

  [0] https://github.com/nukeykt/Nuked-MD-FPGA

• f4pga-examples

  1 260 4.3 Verilog

  Example designs showing different ways to use F4PGA toolchains.

  

• OpenROAD-flow-scripts

  1 252 9.8 Verilog

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  

• wbuart32

  4 246 4.6 Verilog

  A simple, basic, formally verified UART controller

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• FPGA-SDcard-Reader

  1 205 3.8 Verilog

  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

• icestation-32

  1 148 0.0 Verilog

  Compact FPGA game console

  Project mention: The 8-Bit Era: Eight Iconic Processor Designs – By Babbage | news.ycombinator.com | 2023-12-04

  > Or maybe there's a RV32I community for writing retro style games, with some simple graphics support?

  Wow, https://github.com/dan-rodrigues/icestation-32 looks cool. Sorry for the comment spam. :)

• vgasim

  11 147 1.2 Verilog

  A Video display simulator

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• cpu11

  2 146 5.3 Verilog

  Revengineered ancient PDP-11 CPUs, originals and clones

• sdspi

  4 132 7.5 Verilog

  SD-Card controller, using either SPI, SDIO, or eMMC interfaces

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• dspfilters

  2 128 3.5 Verilog

  A collection of demonstration digital filters

• Haasoscope

  1 108 4.8 Verilog

  Docs, design, firmware, and software for the Haasoscope

• dpll

  2 87 2.8 Verilog

  A collection of phase locked loop (PLL) related projects

• SaaSHub

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Verilog Verilog related posts

• FuryGpu – Custom PCIe FPGA GPU
  16 projects | news.ycombinator.com | 27 Mar 2024
• Importance of Open-Source EDA Tools for Academia
  2 projects | news.ycombinator.com | 11 Mar 2024
• Barcelona Supercomputing Center presents Sargantana: new open-source RISC-V chip
  3 projects | news.ycombinator.com | 14 Dec 2023
• SERV – The SErial RISC-V CPU
  1 project | news.ycombinator.com | 10 Dec 2023
• TMNT Arcade Core... WHERE DID IT GO?!
  1 project | /r/MiSTerFPGA | 6 Nov 2023
• OpenROAD
  1 project | news.ycombinator.com | 4 Sep 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  1 project | /r/patient_hackernews | 7 Aug 2023
• A note from our sponsor - WorkOS
  workos.com | 18 Apr 2024

  The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning. Learn more →

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