Top 23 Verilog Verilog Projects

• darkriscv

  0 1,727 0.0 Verilog

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  

• hdl

  1 1,222 0.0 Verilog

  HDL libraries and projects

  

  Project mention: Timing diagram help | /r/FPGA | 2023-03-01

  Have you thought about using ADs source code and pulling what you need to create a front end to their device?

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• zipcpu

  1 1,099 4.1 Verilog

  A small, light weight, RISC CPU soft core

  Project mention: Xilinx FIFO generator for skid buffer? | /r/FPGA | 2022-10-20

  For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.

• serv

  4 1,087 0.0 Verilog

  SERV - The SErial RISC-V CPU

  Project mention: SERV: A bit-serial RISC-V core | news.ycombinator.com | 2023-06-28

• OpenROAD

  5 978 9.9 Verilog

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  

  Project mention: OpenROAD | news.ycombinator.com | 2023-09-04

• riscv

  1 902 1.8 Verilog

  RISC-V CPU Core (RV32IM)

  Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

  I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

• open-fpga-verilog-tutorial

  0 679 0.0 Verilog

  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

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• apio

  2 669 0.0 Verilog

  :seedling: Open source ecosystem for open FPGA boards

  

  Project mention: Looking for help getting started with TinyFPGA | /r/FPGA | 2023-07-08

  apio is a python package you drive from the command line. I didn't know somebody had done an integration with Atom. I've installed and used apio on my phone. I wouldn't really recommend doing that, but it shows what's possible.

• biriscv

  2 644 0.0 Verilog

  32-bit Superscalar RISC-V CPU

  Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• USB_C_Industrial_Camera_FPGA_USB3

  2 603 5.6 Verilog

  Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

  Project mention: Open source USB C icamera with Interchangeable C mount lens, MIPI Sensor | news.ycombinator.com | 2022-12-16

  This is really nice, and the documentation and testing results are extensive.

  https://github.com/circuitvalley/USB_C_Industrial_Camera_FPG...

• OpenTimer

  0 470 0.0 Verilog

  A High-performance Timing Analysis Tool for VLSI Systems

  

• Nuked-MD-FPGA

  5 259 9.4 Verilog

  Mega Drive/Genesis core written in Verilog

  Project mention: Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips | /r/patient_hackernews | 2023-08-07

• f4pga-examples

  0 246 3.2 Verilog

  Example designs showing different ways to use F4PGA toolchains.

  

• wbuart32

  1 223 0.0 Verilog

  A simple, basic, formally verified UART controller

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• FPGA-SDcard-Reader

  1 150 10.0 Verilog

  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

  Project mention: How to read and write data from SD card? | /r/GowinFPGA | 2023-03-21

• vgasim

  1 142 0.0 Verilog

  A Video display simulator

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• cpu11

  0 141 0.0 Verilog

  Revengineered ancient PDP-11 CPUs, originals and clones

• dspfilters

  1 113 1.8 Verilog

  A collection of demonstration digital filters

  Project mention: Looking to implimenting an autocorrelation function (ACF) into one of my projects. | /r/FPGA | 2022-11-24

  Have you considered this article? It goes over the basics of the autocorrelation function, while also illustrating how you can build one with a Wishbone interface. Further, the Verilator logic for this function is kept and maintained on github here. Sure, it uses Wishbone. If you want to use AXI you can either use a bridge, or rework the the interface (it's not that hard ...).

• Haasoscope

  0 107 3.6 Verilog

  Docs, design, firmware, and software for the Haasoscope

• sdspi

  1 93 0.0 Verilog

  SD-Card controller, using a SPI interface that is (optionally) shared

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• dpll

  0 78 0.0 Verilog

  A collection of phase locked loop (PLL) related projects

• wbscope

  0 65 1.8 Verilog

  A wishbone controlled scope for FPGA's

• airisc_core_complex

  1 60 10.0 Verilog

  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

  

  Project mention: A RISC-V processor dedicated for embedded AI | /r/RISCV | 2022-11-10

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Verilog Verilog related posts

• OpenROAD
  1 project | news.ycombinator.com | 4 Sep 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  1 project | /r/patient_hackernews | 7 Aug 2023
• Nuked-MD-FPGA -- cycle-accurate Sega Genesis/MD hardware implementation based on reverse-engineering console's chips
  1 project | /r/bag_o_news | 6 Aug 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  1 project | /r/hackernews | 5 Aug 2023
• Ultraembedded RISCV Module
  1 project | /r/RISCV | 4 Aug 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  3 projects | news.ycombinator.com | 3 Aug 2023
• SERV: A bit-serial RISC-V core
  1 project | news.ycombinator.com | 28 Jun 2023
• A note from our sponsor - Revelo Payroll
  try.revelo.com | 4 Oct 2023

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