Share some github FPGA projects (bonus if they include C++, Python, or other files)

• FPGA_RealTime_and_Static_Sobel_Edge_Detection

  3 37 0.0 Verilog

  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

  I posted this project on this sub three weeks ago,

• InfluxDB

  www.influxdata.com featured

  Purpose built for real-time analytics at any scale. InfluxDB Platform is powered by columnar analytics, optimized for cost-efficient storage, and built with open data standards.

  

• BYU_PYNQ_PR_Video_Pipeline

  2 14 0.0 Jupyter Notebook

  The Demo that was presented at FCCM.

  

• BYU_PYNQ_PR_Video_Pipeline_Hardware

  2 7 0.0 VHDL

  BYU Pynq PR Video Pipeline Hardware

  

• fiate

  4 13 0.0 VHDL

  Fault Injection Automatic Test Equipment

  

• soft_riscv

  1 4 0.0 C

  Soft-core RISCV processor for RISCV 2018 competition

• WARP_Core

  2 7 0.0 VHDL

  Wilson AXI RISCV Processor Core

• satcat5

  25 408 3.8 VHDL

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

  SatCat5 mixed media Ethernet switch

• SaaSHub

  www.saashub.com featured

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

• corundum

  29 1,631 8.3 Verilog

  Open source FPGA-based NIC and platform for in-network compute

  

  100 Gbps capable NIC, intended for research in datacenter networking and in-network computing: https://github.com/corundum/corundum . Includes core logic, designs targeting multiple FPGA boards, Python-based simulation framework, kernel module, and some userspace software.

• verilog-ethernet

  32 2,190 7.8 Verilog

  Verilog Ethernet components for FPGA implementation

  UDP stack for operation up to 25 Gbps: https://github.com/alexforencich/verilog-ethernet . Includes example designs for a number of different boards as well as a Python-based simulation framework.

• xfcp

  5 51 0.0 Verilog

  Extensible FPGA control platform

  Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .

• SBusFPGA

  5 45 5.6 Python

  Stuff to put a FPGA in a SBus system (SPARCstation)

  

  New peripherals on an expansion board for a SPARCstation (90's Sun workstation).

• litex

  29 2,881 9.8 C

  Build your hardware, easily!

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• SpinalHDL

  8 1,613 9.7 Scala

  Scala based HDL

  

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• gateware

  1 27 5.7 Verilog

  IP submodules, formatted for easier CI integration

  

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• verilog-wishbone

  1 106 0.0 Python

  Verilog wishbone components

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• SaaSHub

  www.saashub.com featured

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

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