Share some github FPGA projects (bonus if they include C++, Python, or other files)

• FPGA_RealTime_and_Static_Sobel_Edge_Detection

  1 31 0.0 Verilog

  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

  I posted this project on this sub three weeks ago,

• BYU_PYNQ_PR_Video_Pipeline

  1 14 0.0 Jupyter Notebook

  The Demo that was presented at FCCM.

  

• Mergify

  blog.mergify.com

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• BYU_PYNQ_PR_Video_Pipeline_Hardware

  1 6 0.0 VHDL

  BYU Pynq PR Video Pipeline Hardware

  

• fiate

  0 6 0.0 VHDL

  Fault Injection Automatic Test Equipment

  

• soft_riscv

  0 4 0.0 C

  Soft-core RISCV processor for RISCV 2018 competition

• WARP_Core

  0 6 0.0 VHDL

  Wilson AXI RISCV Processor Core

• satcat5

  11 233 0.0 VHDL

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

  SatCat5 mixed media Ethernet switch

• SonarQube

  www.sonarqube.org

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• corundum

  4 1,283 0.0 Verilog

  Open source FPGA-based NIC and platform for in-network compute

  

  100 Gbps capable NIC, intended for research in datacenter networking and in-network computing: https://github.com/corundum/corundum . Includes core logic, designs targeting multiple FPGA boards, Python-based simulation framework, kernel module, and some userspace software.

• verilog-ethernet

  9 1,641 0.0 Verilog

  Verilog Ethernet components for FPGA implementation

  UDP stack for operation up to 25 Gbps: https://github.com/alexforencich/verilog-ethernet . Includes example designs for a number of different boards as well as a Python-based simulation framework.

• xfcp

  0 47 0.0 Verilog

  Extensible FPGA control platform

  Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .

• SBusFPGA

  1 36 0.0 Python

  Stuff to put a FPGA in a SBus system (SPARCstation)

  New peripherals on an expansion board for a SPARCstation (90's Sun workstation).

• litex

  8 2,356 0.0 C

  Build your hardware, easily!

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• SpinalHDL

  3 1,371 9.5 Scala

  Scala based HDL

  

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• gateware

  0 24 0.0 Verilog

  IP submodules, formatted for easier CI integration

  

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• verilog-wishbone

  0 87 0.0 Python

  Verilog wishbone components

  A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• InfluxDB

  www.influxdata.com

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