Share some github FPGA projects (bonus if they include C++, Python, or other files)

• FPGA_RealTime_and_Static_Sobel_Edge_Detection

  3 34 0.0 Verilog

  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

I posted this project on this sub three weeks ago,

• BYU_PYNQ_PR_Video_Pipeline

  2 14 0.0 Jupyter Notebook

  The Demo that was presented at FCCM.

  

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• BYU_PYNQ_PR_Video_Pipeline_Hardware

  2 7 0.0 VHDL

  BYU Pynq PR Video Pipeline Hardware

  

• fiate

  4 7 0.0 VHDL

  Fault Injection Automatic Test Equipment

  

• soft_riscv

  1 4 0.0 C

  Soft-core RISCV processor for RISCV 2018 competition

• WARP_Core

  2 7 0.0 VHDL

  Wilson AXI RISCV Processor Core

• satcat5

  25 386 3.8 VHDL

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

SatCat5 mixed media Ethernet switch

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• corundum

  28 1,449 9.4 Verilog

  Open source FPGA-based NIC and platform for in-network compute

  

100 Gbps capable NIC, intended for research in datacenter networking and in-network computing: https://github.com/corundum/corundum . Includes core logic, designs targeting multiple FPGA boards, Python-based simulation framework, kernel module, and some userspace software.

• verilog-ethernet

  32 1,888 8.8 Verilog

  Verilog Ethernet components for FPGA implementation

UDP stack for operation up to 25 Gbps: https://github.com/alexforencich/verilog-ethernet . Includes example designs for a number of different boards as well as a Python-based simulation framework.

• xfcp

  5 51 0.0 Verilog

  Extensible FPGA control platform

Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .

• SBusFPGA

  5 43 5.6 Python

  Stuff to put a FPGA in a SBus system (SPARCstation)

New peripherals on an expansion board for a SPARCstation (90's Sun workstation).

• litex

  29 2,672 9.7 C

  Build your hardware, easily!

A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• SpinalHDL

  8 1,506 9.8 Scala

  Scala based HDL

  

A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• gateware

  1 25 5.7 Verilog

  IP submodules, formatted for easier CI integration

  

A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• verilog-wishbone

  1 98 0.0 Python

  Verilog wishbone components

A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)

• SaaSHub

  www.saashub.com sponsored

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

Suggest a related project