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https://github.com/bespoke-silicon-group/basejump_stl maybe?
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CodeRabbit
CodeRabbit: AI Code Reviews for Developers. Revolutionize your code reviews with AI. CodeRabbit offers PR summaries, code walkthroughs, 1-click suggestions, and AST-based analysis. Boost productivity and code quality across all major languages with each PR.
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FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
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Opentitan has a library of well-written system verilog modules here. It's not trying to be a collection for everything one might need, but the superb quality of the code makes it worth to go have a look if there's a chance they may have what you're looking for.
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SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
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satcat5
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
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I think https://www.chisel-lang.org/ which is a high level language that compiles down to Verilog that uses the Scala language as a host. This means you can write components as Scala classes. One of the design goals of Chisel was parametric design reuse, so it should be amenable to an RTL standard library.