Any recommendations for an RTL "standard library"?

• basejump_stl

  1 377 0.0 Verilog

  BaseJump STL: A Standard Template Library for SystemVerilog

  

  https://github.com/bespoke-silicon-group/basejump_stl maybe?

• fusesoc

  1 1,003 8.1 Python

  Package manager and build abstraction tool for FPGA/ASIC development

  FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:

• Mergify

  blog.mergify.com

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• fusesoc-cores

  0 91 0.0

  FuseSoC standard core library

  

• tiny-cores

  0 8 10.0 Verilog

  Collection of assorted small cores

  

• axi

  0 783 0.0 SystemVerilog

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

  Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement

• opentitan

  5 1,957 9.9 SystemVerilog

  OpenTitan: Open source silicon root of trust

  

  Opentitan has a library of well-written system verilog modules here. It's not trying to be a collection for everything one might need, but the superb quality of the code makes it worth to go have a look if there's a chance they may have what you're looking for.

• surf

  0 241 0.0 VHDL

  A huge VHDL library for FPGA development (by slaclab)

  

• SonarQube

  www.sonarqube.org

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• satcat5

  11 232 0.0 VHDL

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

• chisel

  9 3,187 9.4 Scala

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

  I think https://www.chisel-lang.org/ which is a high level language that compiles down to Verilog that uses the Scala language as a host. This means you can write components as Scala classes. One of the design goals of Chisel was parametric design reuse, so it should be amenable to an RTL standard library.

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