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https://github.com/bespoke-silicon-group/basejump_stl maybe?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
Opentitan has a library of well-written system verilog modules here. It's not trying to be a collection for everything one might need, but the superb quality of the code makes it worth to go have a look if there's a chance they may have what you're looking for.
I think https://www.chisel-lang.org/ which is a high level language that compiles down to Verilog that uses the Scala language as a host. This means you can write components as Scala classes. One of the design goals of Chisel was parametric design reuse, so it should be amenable to an RTL standard library.