Trending Verilog Projects

Top 35 Trending Verilog Projects

• OpenROAD-flow-scripts

  1 201 9.0%

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  

• OpenTimer

  2 469 6.4%

  A High-performance Timing Analysis Tool for VLSI Systems

  

• OpenROAD

  3 972 6.4%

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  

• MacroPlacement

  4 158 6.3%

  Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

  

• openc910

  5 894 5.6%

  OpenXuantie - OpenC910 Core

  

• or1200

  6 138 5.1%

  OpenRISC 1200 implementation

  

• openc906

  7 243 4.5%

  OpenXuantie - OpenC906 Core

  

• OpenFPGA

  8 635 4.4%

  An Open-source FPGA IP Generator (by lnis-uofu)

  

• tillitis-key1

  9 308 4.3%

  Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

  

• corundum

  10 1,280 4.2%

  Open source FPGA-based NIC and platform for in-network compute

  

• apicula

  11 345 4.1%

  Project Apicula 🐝: bitstream documentation for Gowin FPGAs

  

• CFU-Playground

  12 408 3.7%

  Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

  

• bsg_manycore

  13 197 3.6%

  Tile based architecture designed for computing efficiency, scalability and generality

  

• betrusted-soc

  14 129 3.1%

  Betrusted main SoC design

  

• vortex

  15 827 3.0%

  

• hw

  16 1,491 2.7%

  RTL, Cmodel, and testbench for NVDLA

  

• fpga

  17 228 2.6%

  The USRP™ Hardware Driver FPGA Repository (by EttusResearch)

  

• hdl

  18 1,218 2.6%

  HDL libraries and projects

  

• NeoGeo_MiSTer

  19 122 2.5%

  NeoGeo for MiSTer

  

• darkriscv

  20 1,726 2.4%

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  

• picorv32

  21 2,528 2.3%

  PicoRV32 - A Size-Optimized RISC-V CPU

  

• livehd

  22 183 2.2%

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  

• basejump_stl

  23 378 2.1%

  BaseJump STL: A Standard Template Library for SystemVerilog

  

• apio

  24 665 2.0%

  :seedling: Open source ecosystem for open FPGA boards

  

• uhd

  25 837 1.9%

  The USRP™ Hardware Driver Repository

  

• ao486_MiSTer

  26 219 1.8%

  ao486 port for MiSTer

  

• SOFA

  27 118 1.7%

  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA (by lnis-uofu)

  

• Minimig-AGA_MiSTer

  28 124 1.6%

  

• f4pga-examples

  29 246 0.8%

  Example designs showing different ways to use F4PGA toolchains.

  

• open-register-design-tool

  30 170 0.6%

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• SCALE-MAMBA

  31 229 0.0%

  Repository for the SCALE-MAMBA MPC system

  

• riscv-formal

  32 489 0.0%

  RISC-V Formal Verification Framework

  

• wujian100_open

  33 1,718 0.0%

  IC design and development should be faster，simpler and more reliable

  

• icebreaker-verilog-examples

  34 126 0.0%

  This repository contains small example designs that can be used with the open source icestorm flow.

  

• netfpga

  35 340 0.0%

  NetFPGA 1G infrastructure and gateware

  

Index