Trending Verilog Projects

Top 40 Trending Verilog Projects

• freepdk-45nm

  1 108 11.1%

  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

  

• umi

  2 109 10.1%

  Universal Memory Interface (UMI) (by zeroasiccorp)

  

• vortex

  3 1,036 6.4%
  

• OpenROAD

  4 1,322 6.0%

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  

• MacroPlacement

  5 193 5.7%

  Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

  

• apicula

  6 420 4.8%

  Project Apicula 🐝: bitstream documentation for Gowin FPGAs

  

• OpenFPGA

  7 742 4.7%

  An Open-source FPGA IP Generator

  

• openc910

  8 1,040 4.2%

  OpenXuantie - OpenC910 Core

  

• hdl

  9 1,374 4.2%

  HDL libraries and projects

  

• OpenROAD-flow-scripts

  10 252 4.0%

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  

• corundum

  11 1,460 3.7%

  Open source FPGA-based NIC and platform for in-network compute

  

• riscv-formal

  12 550 3.6%

  RISC-V Formal Verification Framework

  

• apio

  13 753 3.5%

  :seedling: Open source ecosystem for open FPGA boards

  

• icebreaker-verilog-examples

  14 133 3.0%

  This repository contains small example designs that can be used with the open source icestorm flow.

  

• darkriscv

  15 1,882 2.8%

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  

• uhd

  16 912 2.7%

  The USRP™ Hardware Driver Repository

  

• picorv32

  17 2,763 2.5%

  PicoRV32 - A Size-Optimized RISC-V CPU

  

• fpga

  18 239 2.5%

  The USRP™ Hardware Driver FPGA Repository (by EttusResearch)

  

• openc906

  19 283 2.5%

  OpenXuantie - OpenC906 Core

  

• filament

  20 126 2.4%

  Fearless hardware design (by cucapra)

  

• open-register-design-tool

  21 181 2.2%

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• OpenTimer

  22 511 2.2%

  A High-performance Timing Analysis Tool for VLSI Systems

  

• f4pga-examples

  23 260 1.9%

  Example designs showing different ways to use F4PGA toolchains.

  

• NeoGeo_MiSTer

  24 137 1.5%

  NeoGeo for MiSTer

  

• Minimig-AGA_MiSTer

  25 140 1.4%
  

• ao486_MiSTer

  26 235 1.3%

  ao486 port for MiSTer

  

• wujian100_open

  27 1,786 1.2%

  IC design and development should be faster，simpler and more reliable

  

• netfpga

  28 360 1.1%

  NetFPGA 1G infrastructure and gateware

  

• livehd

  29 197 1.0%

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  

• SCALE-MAMBA

  30 238 0.8%

  Repository for the SCALE-MAMBA MPC system

  

• iob-soc

  31 136 0.7%

  RISC-V System on Chip Template

  

• CFU-Playground

  32 442 0.5%

  Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

  

• tillitis-key1

  33 379 0.3%

  Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

  

• icebreaker-workshop

  34 109 0.0%

  iCEBreaker Workshop

  

• or1200

  35 145 0.0%

  OpenRISC 1200 implementation

  

• miaow

  36 887 0.0%

  An open source GPU based off of the AMD Southern Islands ISA.

  

• SOFA

  37 124 0.0%

  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA (by lnis-uofu)

  

• hw

  38 1,581 0.0%

  RTL, Cmodel, and testbench for NVDLA

  

• C64_MiSTer

  39 110 0.0%
  

• betrusted-soc

  40 132 -0.8%

  Betrusted main SoC design

  

Index