Trending Verilog Projects

This page lists the top trending Verilog projects based on the growth of GitHub stars.
It is updated once every day. The last update was on 30 Sep 2024.
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Top 43 Trending Verilog Projects

  • cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  • freepdk-45nm

    ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

  • umi

    Universal Memory Interface (UMI) (by zeroasiccorp)

  • synlig

    SystemVerilog support for Yosys

  • OpenROAD-flow-scripts

    OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  • miaow

    An open source GPU based off of the AMD Southern Islands ISA.

  • i3c-slave-design

    MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

  • apicula

    Project Apicula šŸ: bitstream documentation for Gowin FPGAs

  • OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  • fpga

    The USRPā„¢ Hardware Driver FPGA Repository (by EttusResearch)

  • icebreaker-verilog-examples

    This repository contains small example designs that can be used with the open source icestorm flow.

  • filament

    Fearless hardware design (by cucapra)

  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • riscv-formal

    RISC-V Formal Verification Framework

  • openc906

    OpenXuantie - OpenC906 Core

  • CFU-Playground

    Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

  • hdl

    HDL libraries and projects

  • corundum

    Open source FPGA-based NIC and platform for in-network compute

  • OpenFPGA

    An Open-source FPGA IP Generator

  • picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

  • ao486_MiSTer

    ao486 port for MiSTer

  • NeoGeo_MiSTer

    NeoGeo for MiSTer

  • openc910

    OpenXuantie - OpenC910 Core

  • wujian100_open

    IC design and development should be fasterļ¼Œsimpler and more reliable

  • vortex

  • uhd

    The USRPā„¢ Hardware Driver Repository

  • Gameboy_MiSTer

    Gameboy for MiSTer

  • C64_MiSTer

  • SOFA

    SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA (by lnis-uofu)

  • tillitis-key1

    Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key šŸ”‘

  • apio

    :seedling: Open source ecosystem for open FPGA boards

  • betrusted-soc

    Betrusted main SoC design

  • Minimig-AGA_MiSTer

  • SCALE-MAMBA

    Repository for the SCALE-MAMBA MPC system

  • hw

    RTL, Cmodel, and testbench for NVDLA

  • icebreaker-workshop

    iCEBreaker Workshop

  • mipsfpga-plus

    MIPSfpga+ allows loading programs via UART and has a switchable clock

  • OpenTimer

    A High-performance Timing Analysis Tool for VLSI Systems

  • netfpga

    NetFPGA 1G infrastructure and gateware

  • f4pga-examples

    Example designs showing different ways to use F4PGA toolchains.

  • MacroPlacement

    Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

  • open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • or1200

    OpenRISC 1200 implementation

ABOUT: The growth percentage is calculated as the increase in the number of stars compared to the previous month. We list only projects that have at least 500 stars and a GitHub organization logo set.

Index

What are some of the trending open-source Verilog projects? This list will help you:

Project Growth
1 cheshire 9.2%
2 freepdk-45nm 7.4%
3 umi 6.6%
4 synlig 5.7%
5 OpenROAD-flow-scripts 4.4%
6 miaow 4.0%
7 i3c-slave-design 3.9%
8 apicula 3.2%
9 OpenROAD 3.1%
10 fpga 3.1%
11 icebreaker-verilog-examples 2.9%
12 filament 2.8%
13 darkriscv 2.5%
14 riscv-formal 2.1%
15 openc906 1.9%
16 CFU-Playground 1.7%
17 hdl 1.7%
18 corundum 1.6%
19 OpenFPGA 1.6%
20 picorv32 1.6%
21 ao486_MiSTer 1.5%
22 NeoGeo_MiSTer 1.4%
23 openc910 1.3%
24 wujian100_open 1.2%
25 vortex 1.1%
26 uhd 1.0%
27 Gameboy_MiSTer 1.0%
28 C64_MiSTer 0.9%
29 SOFA 0.8%
30 tillitis-key1 0.8%
31 apio 0.8%
32 betrusted-soc 0.7%
33 Minimig-AGA_MiSTer 0.7%
34 SCALE-MAMBA 0.4%
35 hw 0.0%
36 icebreaker-workshop 0.0%
37 mipsfpga-plus 0.0%
38 OpenTimer 0.0%
39 netfpga 0.0%
40 f4pga-examples 0.0%
41 MacroPlacement 0.0%
42 open-register-design-tool 0.0%
43 or1200 0.0%