Trending Verilog Projects

Top 10 Trending Verilog Projects

ao486_MiSTer

1 101 8.9%

ao486 port for MiSTer
openlane

2 375 3.5%

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
corundum

3 644 2.5%

Open source, high performance, FPGA-based NIC
hdl

4 802 1.9%

HDL libraries and projects
darkriscv

5 1,153 1.8%

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv-formal

6 352 1.7%

RISC-V Formal Verification Framework
uhd

7 582 1.5%

The USRP™ Hardware Driver Repository
open-register-design-tool

8 138 1.4%

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
livehd

9 120 0.8%

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
basejump_stl

10 197 0.5%

BaseJump STL: A Standard Template Library for SystemVerilog

ABOUT: The growth percentage is calculated as the increase in the number of stars compared to the previous month. We list only projects that have at least 500 stars and a GitHub organization logo set.

Index

What are some of the trending open-source Verilog projects? This list will help you:

	Project	Growth
1	ao486_MiSTer	8.9%
2	openlane	3.5%
3	corundum	2.5%
4	hdl	1.9%
5	darkriscv	1.8%
6	riscv-formal	1.7%
7	uhd	1.5%
8	open-register-design-tool	1.4%
9	livehd	0.8%
10	basejump_stl	0.5%