Trending Verilog Projects

This page lists the top trending Verilog projects based on the growth of GitHub stars.
It is updated once every day. The last update was on 25 Sep 2023.
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Top 35 Trending Verilog Projects

  • OpenROAD-flow-scripts

    OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  • OpenTimer

    A High-performance Timing Analysis Tool for VLSI Systems

  • OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  • MacroPlacement

    Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

  • openc910

    OpenXuantie - OpenC910 Core

  • or1200

    OpenRISC 1200 implementation

  • openc906

    OpenXuantie - OpenC906 Core

  • OpenFPGA

    An Open-source FPGA IP Generator (by lnis-uofu)

  • tillitis-key1

    Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

  • corundum

    Open source FPGA-based NIC and platform for in-network compute

  • apicula

    Project Apicula 🐝: bitstream documentation for Gowin FPGAs

  • CFU-Playground

    Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

  • bsg_manycore

    Tile based architecture designed for computing efficiency, scalability and generality

  • betrusted-soc

    Betrusted main SoC design

  • vortex

  • hw

    RTL, Cmodel, and testbench for NVDLA

  • fpga

    The USRP™ Hardware Driver FPGA Repository (by EttusResearch)

  • hdl

    HDL libraries and projects

  • NeoGeo_MiSTer

    NeoGeo for MiSTer

  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

  • livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  • basejump_stl

    BaseJump STL: A Standard Template Library for SystemVerilog

  • apio

    :seedling: Open source ecosystem for open FPGA boards

  • uhd

    The USRP™ Hardware Driver Repository

  • ao486_MiSTer

    ao486 port for MiSTer

  • SOFA

    SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA (by lnis-uofu)

  • f4pga-examples

    Example designs showing different ways to use F4PGA toolchains.

  • open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • SCALE-MAMBA

    Repository for the SCALE-MAMBA MPC system

  • riscv-formal

    RISC-V Formal Verification Framework

  • wujian100_open

    IC design and development should be faster,simpler and more reliable

  • icebreaker-verilog-examples

    This repository contains small example designs that can be used with the open source icestorm flow.

  • netfpga

    NetFPGA 1G infrastructure and gateware

ABOUT: The growth percentage is calculated as the increase in the number of stars compared to the previous month. We list only projects that have at least 500 stars and a GitHub organization logo set.

Index

What are some of the trending open-source Verilog projects? This list will help you:

Project Growth
1 OpenROAD-flow-scripts 9.0%
2 OpenTimer 6.4%
3 OpenROAD 6.4%
4 MacroPlacement 6.3%
5 openc910 5.6%
6 or1200 5.1%
7 openc906 4.5%
8 OpenFPGA 4.4%
9 tillitis-key1 4.3%
10 corundum 4.2%
11 apicula 4.1%
12 CFU-Playground 3.7%
13 bsg_manycore 3.6%
14 betrusted-soc 3.1%
15 vortex 3.0%
16 hw 2.7%
17 fpga 2.6%
18 hdl 2.6%
19 NeoGeo_MiSTer 2.5%
20 darkriscv 2.4%
21 picorv32 2.3%
22 livehd 2.2%
23 basejump_stl 2.1%
24 apio 2.0%
25 uhd 1.9%
26 ao486_MiSTer 1.8%
27 SOFA 1.7%
28 Minimig-AGA_MiSTer 1.6%
29 f4pga-examples 0.8%
30 open-register-design-tool 0.6%
31 SCALE-MAMBA 0.0%
32 riscv-formal 0.0%
33 wujian100_open 0.0%
34 icebreaker-verilog-examples 0.0%
35 netfpga 0.0%