Trending Verilog Projects

This page lists the top trending projects based on the growth of GitHub stars.
It is updated once every week. The last update was on 2 Aug 2021.
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Top 10 Trending Verilog Projects

  • GitHub repo ao486_MiSTer

    ao486 port for MiSTer

  • GitHub repo openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

  • GitHub repo corundum

    Open source, high performance, FPGA-based NIC

  • GitHub repo hdl

    HDL libraries and projects

  • GitHub repo darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • GitHub repo riscv-formal

    RISC-V Formal Verification Framework

  • GitHub repo uhd

    The USRP™ Hardware Driver Repository

  • GitHub repo open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • GitHub repo livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  • GitHub repo basejump_stl

    BaseJump STL: A Standard Template Library for SystemVerilog

ABOUT: The growth percentage is calculated as the increase in the number of stars compared to the previous month. We list only projects that have at least 500 stars and a GitHub organization logo set.

Index

What are some of the trending open-source Verilog projects? This list will help you:

Project Growth
1 ao486_MiSTer 8.9%
2 openlane 3.5%
3 corundum 2.5%
4 hdl 1.9%
5 darkriscv 1.8%
6 riscv-formal 1.7%
7 uhd 1.5%
8 open-register-design-tool 1.4%
9 livehd 0.8%
10 basejump_stl 0.5%