Top 23 Verilog Fpga Projects

• darkriscv

  0 1,796 0.0 Verilog

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  

• corundum

  1 1,349 0.0 Verilog

  Open source FPGA-based NIC and platform for in-network compute

  

  Project mention: TCP checksum computation | /r/FPGA | 2023-05-21

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• hdl

  1 1,263 0.0 Verilog

  HDL libraries and projects

  

  Project mention: Timing diagram help | /r/FPGA | 2023-03-01

  Have you thought about using ADs source code and pulling what you need to create a front end to their device?

• serv

  2 1,135 0.0 Verilog

  SERV - The SErial RISC-V CPU

  Project mention: SERV: A bit-serial RISC-V core | news.ycombinator.com | 2023-06-28

• zipcpu

  0 1,123 1.8 Verilog

  A small, light weight, RISC CPU soft core

• riscv

  1 902 1.8 Verilog

  RISC-V CPU Core (RV32IM)

  Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

  I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

• uhd

  0 862 9.4 Verilog

  The USRP™ Hardware Driver Repository

  

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• open-fpga-verilog-tutorial

  0 704 0.0 Verilog

  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

• apio

  2 680 0.0 Verilog

  :seedling: Open source ecosystem for open FPGA boards

  

  Project mention: Looking for help getting started with TinyFPGA | /r/FPGA | 2023-07-08

  apio is a python package you drive from the command line. I didn't know somebody had done an integration with Atom. I've installed and used apio on my phone. I wouldn't really recommend doing that, but it shows what's possible.

• OpenFPGA

  0 666 0.0 Verilog

  An Open-source FPGA IP Generator (by lnis-uofu)

  

• biriscv

  2 644 0.0 Verilog

  32-bit Superscalar RISC-V CPU

  Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• USB_C_Industrial_Camera_FPGA_USB3

  2 629 4.2 Verilog

  Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

  Project mention: Open source USB C icamera with Interchangeable C mount lens, MIPI Sensor | news.ycombinator.com | 2022-12-16

  This is really nice, and the documentation and testing results are extensive.

  https://github.com/circuitvalley/USB_C_Industrial_Camera_FPG...

• wb2axip

  2 389 0.0 Verilog

  Bus bridges and other odds and ends

  Project mention: Simple skid buffer implementation | /r/FPGA | 2023-01-10

  I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)

• tillitis-key1

  4 312 8.5 Verilog

  Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

  

  Project mention: Fixing the TPM: Hardware Security Modules Done Right | news.ycombinator.com | 2023-08-18

  Having a look at their documented threat model: https://github.com/tillitis/tillitis-key1/blob/main/doc/thre...

  I love this particular detail, listed under Assumptions:

  > The end user is not an attacker. The end user at least doesn't knowingly aid the attacker in attacks on their device.

  I love this, it's exactly what I want from a HSM device. However, sadly, most vendors today deploy TPMs in such a way that the end-user is an attacker (see: Google SafetyNet) - and the TKey is kinda incompatible with that, I suppose.

• Nuked-MD-FPGA

  6 265 9.3 Verilog

  Mega Drive/Genesis core written in Verilog

  Project mention: FPGAs and the Renaissance of Retro Hardware | news.ycombinator.com | 2023-11-27

  The reality is that the vast majority of these FPGA-based clones don't actually perfectly emulate the logic. They're using the same reverse engineering techniques the traditional emulator developers used and sometimes even the same community documentation. The results are often quite good, but they're making a new implementation that matches the observed behavior of the original system to the best of their abilities.

  Now there are some exceptions. Nuked MD FPGA[0] is a recent example of an FPGA recreation that is a fairly direct translation of the original logic using silicon die analysis. In this case, the logic is basically identical, but as you guessed the physical layout is different. Generally speaking, you write FPGA "gateware" in a language like Verilog or VHDL. These don't intrinsically have any information about the physical layout of the logic which is handled by the toolchain instead. As wmf says, this is generally not a problem most of the time. For synchronous logic, either the total propagation delay is small enough for a single cycle or it isn't. The toolchain will estimate this delay and report whether you met timing or not for the configured clockspeed.

  Not everything you can do in silicon translates well to FPGAs (both clock edges is also generally not well supported for instance), but for the most part these things are easy enough to work around.

  [0] https://github.com/nukeykt/Nuked-MD-FPGA

• f4pga-examples

  0 247 0.0 Verilog

  Example designs showing different ways to use F4PGA toolchains.

  

• wbuart32

  1 229 0.0 Verilog

  A simple, basic, formally verified UART controller

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• nestang

  2 212 10.0 Verilog

  NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

  Project mention: Gaming on less-expensive FPGAs? | /r/fpgagaming | 2022-12-19

• livehd

  0 186 0.0 Verilog

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  

• open-register-design-tool

  0 174 0.0 Verilog

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• FPGA-SDcard-Reader

  1 158 10.0 Verilog

  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

  Project mention: How to read and write data from SD card? | /r/GowinFPGA | 2023-03-21

• vgasim

  1 144 0.0 Verilog

  A Video display simulator

  Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

  I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• dspfilters

  0 113 1.8 Verilog

  A collection of demonstration digital filters

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Verilog Fpga related posts

• TMNT Arcade Core... WHERE DID IT GO?!
  1 project | /r/MiSTerFPGA | 6 Nov 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  1 project | /r/patient_hackernews | 7 Aug 2023
• Nuked-MD-FPGA -- cycle-accurate Sega Genesis/MD hardware implementation based on reverse-engineering console's chips
  1 project | /r/bag_o_news | 6 Aug 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  1 project | /r/hackernews | 5 Aug 2023
• Ultraembedded RISCV Module
  1 project | /r/RISCV | 4 Aug 2023
• Nuked-MD-FPGA – accurate Sega Genesis re-implementation based on decapped chips
  3 projects | news.ycombinator.com | 3 Aug 2023
• Looking for help getting started with TinyFPGA
  1 project | /r/FPGA | 8 Jul 2023
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