Verilog Fpga

Open-source Verilog projects categorized as Fpga Edit details

Top 23 Verilog Fpga Projects

  • hdl

    HDL libraries and projects

    Project mention: Vivado 2020.2 IP Repository Suggestion | reddit.com/r/FPGA | 2022-02-28
  • corundum

    Open source FPGA-based NIC and platform for in-network compute

    Project mention: shift/concatenate in v/sv | reddit.com/r/FPGA | 2022-08-08

    I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.

  • SonarLint

    Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.

  • zipcpu

    A small, light weight, RISC CPU soft core

    Project mention: What make xilinx fpga runs soft core cpu faster than lattice | reddit.com/r/FPGA | 2022-03-27

    check out this usage chart for the ZipCPU's logic usage (also linked above). Each line in the chart beginning with Zip represents a different CPU configuration. If the FPGA speeds were the same (they aren't typically), then each configuration line should have the same CPU speed (not counting interconnect, RAM or peripherals). Two of the columns measure iCE40 4-LUTs and Xilinx 6-LUTs.

  • serv

    SERV - The SErial RISC-V CPU

    Project mention: RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021 | news.ycombinator.com | 2022-06-21

    The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.

    https://github.com/olofk/serv#good-to-know

  • uhd

    The USRP™ Hardware Driver Repository

  • open-fpga-verilog-tutorial

    Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

  • riscv

    RISC-V CPU Core (RV32IM) (by ultraembedded)

    Project mention: I made my own silicon chip: Project Silicon Rider | news.ycombinator.com | 2021-10-03
  • Scout APM

    Less time debugging, more time building. Scout APM allows you to find and fix performance issues with no hassle. Now with error monitoring and external services monitoring, Scout is a developer's best friend when it comes to application development.

  • apio

    :seedling: Open source ecosystem for open FPGA boards

  • biriscv

    32-bit Superscalar RISC-V CPU

  • wb2axip

    Bus bridges and other odds and ends

    Project mention: Implement Synchronous FWFT FIFO in BRAM | reddit.com/r/FPGA | 2022-07-07

    Here's an example of an FWFT FIFO written in a vendor independent fashion. Yes, it requires a bit of wizardry to get right--primarily in how the read address is calculated, but I've used it for years now and it's held up nicely for me.

  • f4pga-examples

    Example designs showing different ways to use F4PGA toolchains.

    Project mention: Symbiflow: The GCC of the FPGA World | news.ycombinator.com | 2021-09-28
  • wbuart32

    A simple, basic, formally verified UART controller

    Project mention: CDC interview question clarification | reddit.com/r/FPGA | 2022-05-22

    Try this one.

  • livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  • open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • vgasim

    A Video display simulator

    Project mention: Sobel algorithm in VHDL help | reddit.com/r/FPGA | 2022-05-17

    Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.

  • antikernel

    The Antikernel operating system project

  • openarty

    An Open Source configuration of the Arty platform

    Project mention: PPS detection/regeneration | reddit.com/r/FPGA | 2022-05-25

    The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.

  • dspfilters

    A collection of demonstration digital filters

    Project mention: Professional or Hobby? | reddit.com/r/FPGA | 2022-01-08

    I marked as "both" above, but one might argue that my "hobby" designs are more "Internal Research and Development" (IR&D) than just hobby. Everything has a purpose. Today's hobby design may be used in tomorrow's paying project. Examples include the both the ZipCPU and its subcomponents, my AXI work, DSP filters, PLLs, FFT and much more--all of which have found their way into a variety of customer designs.

  • Haasoscope

    Docs, design, firmware, and software for the Haasoscope

  • ice-chips-verilog

    IceChips is a library of all common discrete logic devices in Verilog

  • sdspi

    SD-Card controller, using a SPI interface that is (optionally) shared

    Project mention: Envisioning the Ultimate I2C Controller | reddit.com/r/ZipCPU | 2021-11-18

    You mean ... sort of like I did in this project? I implemented an SPI based controller, where the controller took care of all the bit-banging for you, but the CPU still needed to issue the commands as appropriate for the protocol?

  • dpll

    A collection of phase locked loop (PLL) related projects

    Project mention: PLL simulation in Vivado | reddit.com/r/FPGA | 2022-08-10

    For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.

  • wbscope

    A wishbone controlled scope for FPGA's

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2022-08-10.

Verilog Fpga related posts

Index

What are some of the best open-source Fpga projects in Verilog? This list will help you:

Project Stars
1 hdl 994
2 corundum 911
3 zipcpu 883
4 serv 788
5 uhd 694
6 open-fpga-verilog-tutorial 577
7 riscv 573
8 apio 547
9 biriscv 423
10 wb2axip 305
11 f4pga-examples 206
12 wbuart32 174
13 livehd 154
14 open-register-design-tool 151
15 vgasim 110
16 antikernel 106
17 openarty 94
18 dspfilters 93
19 Haasoscope 92
20 ice-chips-verilog 78
21 sdspi 68
22 dpll 60
23 wbscope 60
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