Top 23 Verilog Fpga Projects

• hdl

  2 994 9.3 Verilog

  HDL libraries and projects

  

  Project mention: Vivado 2020.2 IP Repository Suggestion | reddit.com/r/FPGA | 2022-02-28

• corundum

  13 911 9.7 Verilog

  Open source FPGA-based NIC and platform for in-network compute

  

  Project mention: shift/concatenate in v/sv | reddit.com/r/FPGA | 2022-08-08

  I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.

• SonarLint

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• zipcpu

  3 883 1.9 Verilog

  A small, light weight, RISC CPU soft core

  Project mention: What make xilinx fpga runs soft core cpu faster than lattice | reddit.com/r/FPGA | 2022-03-27

  check out this usage chart for the ZipCPU's logic usage (also linked above). Each line in the chart beginning with Zip represents a different CPU configuration. If the FPGA speeds were the same (they aren't typically), then each configuration line should have the same CPU speed (not counting interconnect, RAM or peripherals). Two of the columns measure iCE40 4-LUTs and Xilinx 6-LUTs.

• serv

  9 788 7.3 Verilog

  SERV - The SErial RISC-V CPU

  Project mention: RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021 | news.ycombinator.com | 2022-06-21

  The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.

  https://github.com/olofk/serv#good-to-know

• uhd

  0 694 9.8 Verilog

  The USRP™ Hardware Driver Repository

  

• open-fpga-verilog-tutorial

  0 577 0.0 Verilog

  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

• riscv

  1 573 0.7 Verilog

  RISC-V CPU Core (RV32IM) (by ultraembedded)

  Project mention: I made my own silicon chip: Project Silicon Rider | news.ycombinator.com | 2021-10-03

• Scout APM

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• apio

  0 547 8.3 Verilog

  :seedling: Open source ecosystem for open FPGA boards

  

• biriscv

  0 423 0.7 Verilog

  32-bit Superscalar RISC-V CPU

• wb2axip

  18 305 6.8 Verilog

  Bus bridges and other odds and ends

  Project mention: Implement Synchronous FWFT FIFO in BRAM | reddit.com/r/FPGA | 2022-07-07

  Here's an example of an FWFT FIFO written in a vendor independent fashion. Yes, it requires a bit of wizardry to get right--primarily in how the read address is calculated, but I've used it for years now and it's held up nicely for me.

• f4pga-examples

  1 206 9.2 Verilog

  Example designs showing different ways to use F4PGA toolchains.

  

  Project mention: Symbiflow: The GCC of the FPGA World | news.ycombinator.com | 2021-09-28

• wbuart32

  2 174 0.0 Verilog

  A simple, basic, formally verified UART controller

  Project mention: CDC interview question clarification | reddit.com/r/FPGA | 2022-05-22

  Try this one.

• livehd

  0 154 9.4 Verilog

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  

• open-register-design-tool

  0 151 0.0 Verilog

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• vgasim

  3 110 0.0 Verilog

  A Video display simulator

  Project mention: Sobel algorithm in VHDL help | reddit.com/r/FPGA | 2022-05-17

  Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.

• antikernel

  0 106 0.0 Verilog

  The Antikernel operating system project

• openarty

  4 94 1.0 Verilog

  An Open Source configuration of the Arty platform

  Project mention: PPS detection/regeneration | reddit.com/r/FPGA | 2022-05-25

  The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.

• dspfilters

  1 93 4.0 Verilog

  A collection of demonstration digital filters

  Project mention: Professional or Hobby? | reddit.com/r/FPGA | 2022-01-08

  I marked as "both" above, but one might argue that my "hobby" designs are more "Internal Research and Development" (IR&D) than just hobby. Everything has a purpose. Today's hobby design may be used in tomorrow's paying project. Examples include the both the ZipCPU and its subcomponents, my AXI work, DSP filters, PLLs, FFT and much more--all of which have found their way into a variety of customer designs.

• Haasoscope

  0 92 6.0 Verilog

  Docs, design, firmware, and software for the Haasoscope

• ice-chips-verilog

  0 78 0.0 Verilog

  IceChips is a library of all common discrete logic devices in Verilog

• sdspi

  1 68 0.0 Verilog

  SD-Card controller, using a SPI interface that is (optionally) shared

  Project mention: Envisioning the Ultimate I2C Controller | reddit.com/r/ZipCPU | 2021-11-18

  You mean ... sort of like I did in this project? I implemented an SPI based controller, where the controller took care of all the bit-banging for you, but the CPU still needed to issue the commands as appropriate for the protocol?

• dpll

  1 60 0.0 Verilog

  A collection of phase locked loop (PLL) related projects

  Project mention: PLL simulation in Vivado | reddit.com/r/FPGA | 2022-08-10

  For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.

• wbscope

  0 60 0.4 Verilog

  A wishbone controlled scope for FPGA's

Verilog Fpga related posts

• PLL simulation in Vivado
  1 project | reddit.com/r/FPGA | 10 Aug 2022
• shift/concatenate in v/sv
  1 project | reddit.com/r/FPGA | 8 Aug 2022
• Can an FPGA program itself?
  1 project | reddit.com/r/FPGA | 21 Jul 2022
• Implement Synchronous FWFT FIFO in BRAM
  1 project | reddit.com/r/FPGA | 7 Jul 2022
• PPS detection/regeneration
  2 projects | reddit.com/r/FPGA | 25 May 2022
• CDC interview question clarification
  1 project | reddit.com/r/FPGA | 22 May 2022
• Efinix and Xyloni Board - Heard a lot of clients mention them, so took a look.
  1 project | reddit.com/r/FPGA | 22 May 2022

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