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Are there any dual-GBE, PoE-capable SBCs?
2 projects | /r/linuxhardware | 20 Aug 2021
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
5 projects | /r/linux | 26 Jun 2021
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
Looking for a RISC-V core for verification
3 projects | /r/RISCV | 18 May 2022
SweRV EH1 comes with a verilator testbench that can run compiled instructions. You'll need to expand on it if you want things like external memory etc.
Nvidia: GPUs can do better chip design in a few days than 10 man year
2 projects | news.ycombinator.com | 19 Apr 2022
together foundations and the use domains of chip design, networks and robotics; (iii) the cycle of translation and impact brings research and the leading edge of practice closer together; and (iv) the cycle of research, education, and broadening participation grows the field and its workforce.*
The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking.
There are plenty of company's releasing the chips too. Google's OpenTitan security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others.
I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them.
Is a single cycle CPU of any use besides learning?
4 projects | /r/RISCV | 31 Oct 2021
Absolutely! I have no illusions that I'll build anything even remotely comparable to a commercial core. I had a look at the features of the WD SweRV core and the complexity simply blows my mind, I don't think I'll get there any time soon. This is purely for fun, but it will be much more satisfying if I can start using the CPU I designed in my tiny personal IoT projects. Hence the question, at what point can I start finding some use for it. Maybe an arduino replacement?
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
4 projects | /r/hardware | 8 Sep 2021
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
About RISC-V becoming so popular as ARM for Embedded Systems
2 projects | /r/embedded | 28 Feb 2021
Per your last point, I believe this is the most important one. Big vendors like WD can just design their own core and plop it down in all of their hard drives that ship in large volumes. They even share their RTL.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
Cores-VeeR-EL2 - VeeR EL2 Core
riscv - RISC-V CPU Core (RV32IM)
rocket-chip - Rocket Chip Generator
friscv - RISCV CPU implementation in SystemVerilog
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform