darkriscv
Cores-VeeR-EH1
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darkriscv | Cores-VeeR-EH1 | |
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3 | 8 | |
1,873 | 773 | |
2.3% | 1.6% | |
6.8 | 0.0 | |
3 months ago | 11 months ago | |
Verilog | SystemVerilog | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
Cores-VeeR-EH1
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Looking for a RISC-V core for verification
SweRV EH1 comes with a verilator testbench that can run compiled instructions. You'll need to expand on it if you want things like external memory etc.
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Nvidia: GPUs can do better chip design in a few days than 10 man year
together foundations and the use domains of chip design, networks and robotics; (iii) the cycle of translation and impact brings research and the leading edge of practice closer together; and (iv) the cycle of research, education, and broadening participation grows the field and its workforce.*
The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking.
There are plenty of company's releasing the chips too. Google's OpenTitan[2] security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement[3]. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others.
I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them.
[1] https://theopenroadproject.org/news/leveling-up-a-trajectory...
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Is a single cycle CPU of any use besides learning?
Absolutely! I have no illusions that I'll build anything even remotely comparable to a commercial core. I had a look at the features of the WD SweRV core and the complexity simply blows my mind, I don't think I'll get there any time soon. This is purely for fun, but it will be much more satisfying if I can start using the CPU I designed in my tiny personal IoT projects. Hence the question, at what point can I start finding some use for it. Maybe an arduino replacement?
- How does philosophy of open source hardware react to "dominant" chip makers?
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
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Nvidia's ownership of ARM could drive customers to RISC-V, other alternatives if not careful, says Xilinx CEO
This act is probably the single biggest driver of immediate term adoption of RISC-V. Western Digital creating their own RISC-V chip and open sourcing it hurt either.
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About RISC-V becoming so popular as ARM for Embedded Systems
Per your last point, I believe this is the most important one. Big vendors like WD can just design their own core and plop it down in all of their hard drives that ship in large volumes. They even share their RTL.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
XiangShan - Open-source high-performance RISC-V processor
Cores-VeeR-EL2 - VeeR EL2 Core
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
rocket-chip - Rocket Chip Generator
riscv - RISC-V CPU Core (RV32IM)
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
friscv - RISCV CPU implementation in SystemVerilog
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs