SystemVerilog IP

Open-source SystemVerilog projects categorized as IP
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Topics: Fpga Hardware Asic Verilog Rtl
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Top 3 SystemVerilog IP Projects

  • axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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  • libsv

    An open source, parameterized SystemVerilog digital hardware IP library

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

SystemVerilog IP related posts

  • Skid Buffer

    1 project | /r/FPGA | 23 Jul 2022

Index

What are some of the best open-source IP projects in SystemVerilog? This list will help you:

Project Stars
1 axi 930
2 scr1 776
3 libsv 19

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