Top 7 SystemVerilog Rtl Projects

axi

3 920 6.8 SystemVerilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Cores-VeeR-EH1

8 773 0.0 SystemVerilog

VeeR EH1 core
InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
scr1

2 768 3.3 SystemVerilog

SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Cores-VeeR-EL2

1 222 9.2 SystemVerilog

VeeR EL2 Core
rggen-sv-rtl

1 10 4.7 SystemVerilog

Common SystemVerilog RTL modules for RgGen
Arithmetic-Circuits

1 3 3.8 SystemVerilog

This repository contains different modules which execute arithmetic operations. (by GabbedT)
RTLDesignSherpa

1 1 9.5 SystemVerilog

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

Project mention: Weighted round robin | /r/FPGA | 2023-12-07

WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-12-07.