Trending SystemVerilog Projects

Top 21 Trending SystemVerilog Projects

• cheshire

  1 107 10.3%

  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  

• projf-explore

  2 526 5.7%

  Project F brings FPGAs to life with exciting open-source designs you can build on.

  

• Coyote

  3 181 5.5%

  Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms. (by fpgasystems)

  

• NES_MiSTer

  4 164 3.7%
  

• black-parrot

  5 536 3.5%

  A Linux-capable RISC-V multicore for and by the world

  

• rsd

  6 919 3.5%

  RSD: RISC-V Out-of-Order Superscalar Processor

  

• axi

  7 933 3.3%

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• eurorack-pmod

  8 159 3.1%

  A eurorack-friendly audio frontend compatible with many FPGA boards.

  

• cvfpu

  9 364 2.5%

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  

• ibex

  10 1,257 2.5%

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

• basejump_stl

  11 448 2.2%

  BaseJump STL: A Standard Template Library for SystemVerilog

  

• hdmi

  12 1,014 1.9%

  Send video/audio over HDMI on an FPGA

  

• cv32e40p

  13 876 1.7%

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  

• opentitan

  14 2,365 1.6%

  OpenTitan: Open source silicon root of trust

  

• scr1

  15 776 1.4%

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  

• Cores-VeeR-EL2

  16 222 0.9%

  VeeR EL2 Core

  

• Cores-VeeR-EH1

  17 774 0.8%

  VeeR EH1 core

  

• lowrisc-chip

  18 584 0.7%

  The root repo for lowRISC project and FPGA demos.

  

• bsg_manycore

  19 211 0.5%

  Tile based architecture designed for computing efficiency, scalability and generality

  

• Cores-VeeR-EH2

  20 202 0.0%
  

• pulpissimo

  21 332 0.0%

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  

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