Trending SystemVerilog Projects

Top 20 Trending SystemVerilog Projects

• Coyote

  1 137 9.5%

  Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms. (by fpgasystems)

  

• axi

  2 788 6.5%

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• cvfpu

  3 310 5.8%

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  

• eurorack-pmod

  4 121 5.8%

  Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.

  

• projf-explore

  5 449 4.9%

  Project F brings FPGAs to life with exciting open-source designs you can build on.

  

• cv32e40p

  6 776 4.8%

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  

• Cores-VeeR-EL2

  7 191 4.7%

  VeeR EL2 Core

  

• black-parrot

  8 443 4.5%

  A Linux-capable RISC-V multicore for and by the world

  

• ibex

  9 1,084 4.3%

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

• Cores-VeeR-EH1

  10 727 3.2%

  VeeR EH1 core

  

• Cores-VeeR-EH2

  11 189 2.6%

  

• pulpissimo

  12 313 2.6%

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  

• cva6

  13 1,829 2.4%

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  

• scr1

  14 688 2.3%

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  

• snitch

  15 206 1.9%

  Lean but mean RISC-V system! (by pulp-platform)

  

• opentitan

  16 1,959 1.9%

  OpenTitan: Open source silicon root of trust

  

• rsd

  17 815 1.6%

  RSD: RISC-V Out-of-Order Superscalar Processor

  

• hdmi

  18 901 1.3%

  Send video/audio over HDMI on an FPGA

  

• lowrisc-chip

  19 560 1.1%

  The root repo for lowRISC project and FPGA demos.

  

• NES_MiSTer

  20 136 0.0%

  

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