Trending SystemVerilog Projects

Top 50 Trending SystemVerilog Projects

1. Coyote

   1 389 10.8%

   Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms. (by fpgasystems)

   

2. tiny-gpu

   2 12,389 7.3%

   A minimal GPU design in Verilog to learn how GPUs work from the ground up

   

3. HaDes-V

   3 165 5.5%

   HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

   

4. VeriGPU

   4 1,317 4.6%

   OpenSource GPU, in Verilog, loosely based on RISC-V ISA

   

5. SoomRV

   5 248 4.4%

   A simple superscalar out-of-order RISC-V microprocessor

   

6. cgra4ml

   6 120 4.2%

   An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

   

7. baochip-1x

   7 362 3.6%

   Baochip 1x Silicon

   

8. cvw

   8 543 3.5%

   CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

   

9. tiny-tpu-old

   9 200 3.0%

   A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.

   

10. sargantana

    10 139 2.9%

    

11. verilator

    11 3,675 2.8%

    Verilator open-source SystemVerilog simulator and lint system

    

12. riscv-ocelot

    12 253 2.8%

    Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

    

13. opentitan

    13 3,447 2.7%

    OpenTitan: Open source silicon root of trust

    

14. cvfpu

    14 609 2.5%

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    

15. ibex

    15 1,904 2.4%

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    

16. MinecraftHDL

    16 1,556 1.9%

    A Verilog synthesis flow for Minecraft redstone circuits

    

17. Cores-VeeR-EH1

    17 945 1.9%

    VeeR EH1 core

    

18. scr1

    18 980 1.8%

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    

19. axi

    19 1,589 1.8%

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    

20. FazyRV

    20 116 1.7%

    A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

    

21. bsg_manycore

    21 293 1.7%

    Tile based architecture designed for computing efficiency, scalability and generality

    

22. cv32e40p

    22 1,242 1.7%

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    

23. pulpissimo

    23 483 1.7%

    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

    

24. black-parrot

    24 810 1.6%

    A Linux-capable RISC-V multicore for and by the world

    

25. ravenoc

    25 192 1.6%

    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

    

26. hdmi

    26 1,265 1.3%

    Send video/audio over HDMI on an FPGA

    

27. basejump_stl

    27 668 1.2%

    BaseJump STL: A Standard Template Library for SystemVerilog

    

28. fpga-tamagotchi

    28 170 1.2%

    Tamagotchi P1 for Analogue Pocket and MiSTer

    

29. projf-explore

    29 772 1.2%

    Project F brings FPGAs to life with exciting open-source designs you can build on.

    

30. NES_MiSTer

    30 199 1.0%

    

31. Cores-VeeR-EL2

    31 338 0.9%

    VeeR EL2 Core

    

32. eurorack-pmod

    32 233 0.9%

    A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

    

33. rsd

    33 1,179 0.8%

    RSD: RISC-V Out-of-Order Superscalar Processor

    

34. lets-prove-leftpad

    34 734 0.8%

    Proving leftpad correct two-dozen different ways

    

35. cheriot-ibex

    35 130 0.8%

    cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

    

36. aws-fpga

    36 1,665 0.6%

    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

    

37. opl3_fpga

    37 402 0.5%

    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

    

38. openfpga-NES

    38 214 0.5%

    NES for the Analogue Pocket

    

39. muntjac

    39 111 0.0%

    64-bit multicore Linux-capable RISC-V processor (by lowRISC)

    

40. lowrisc-chip

    40 601 0.0%

    The root repo for lowRISC project and FPGA demos.

    

41. NiteFury-and-LiteFury

    41 316 0.0%

    Public repository for Litefury & Nitefury

    

42. Cores-VeeR-EH2

    42 261 0.0%

    

43. mega-ed-pub

    43 111 0.0%

    Mega EverDrive dev sources

    

44. riscv-simple-sv

    44 202 0.0%

    A simple RISC V core for teaching

    

45. starshipraider

    45 192 0.0%

    Open hardware test equipment

    

46. AHB2

    46 160 0.0%

    AMBA AHB 2.0 VIP in SystemVerilog UVM

    

47. uvmprimer

    47 611 0.0%

    Contains the code examples from The UVM Primer Book sorted by chapters.

    

48. open-nic-shell

    48 136 0.0%

    AMD OpenNIC Shell includes the HDL source files

    

49. analogue-pocket-utils

    49 126 0.0%

    Collection of IP and information on how to develop for openFPGA and Analogue Pocket

    

50. wav-lpddr-hw

    50 126 0.0%

    Wavious DDR (WDDR) Physical interface (PHY) Hardware

    

Index