Trending SystemVerilog Projects

This page lists the top trending SystemVerilog projects based on the growth of GitHub stars.
It is updated once every day. The last update was on 22 Jul 2024.
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Top 20 Trending SystemVerilog Projects

  • Cores-VeeR-EL2

    VeeR EL2 Core

  • cvfpu

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  • basejump_stl

    BaseJump STL: A Standard Template Library for SystemVerilog

  • Coyote

    Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms. (by fpgasystems)

  • black-parrot

    A Linux-capable RISC-V multicore for and by the world

  • axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • projf-explore

    Project F brings FPGAs to life with exciting open-source designs you can build on.

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • pulpissimo

    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  • eurorack-pmod

    A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

  • ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  • opentitan

    OpenTitan: Open source silicon root of trust

  • hdmi

    Send video/audio over HDMI on an FPGA

  • cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  • NES_MiSTer

  • Cores-VeeR-EH2

  • rsd

    RSD: RISC-V Out-of-Order Superscalar Processor

  • bsg_manycore

    Tile based architecture designed for computing efficiency, scalability and generality

  • lowrisc-chip

    The root repo for lowRISC project and FPGA demos.

  • Cores-VeeR-EH1

    VeeR EH1 core

ABOUT: The growth percentage is calculated as the increase in the number of stars compared to the previous month. We list only projects that have at least 500 stars and a GitHub organization logo set.


What are some of the trending open-source SystemVerilog projects? This list will help you:

Project Growth
1 Cores-VeeR-EL2 6.3%
2 cvfpu 6.2%
3 basejump_stl 5.2%
4 Coyote 4.6%
5 black-parrot 4.4%
6 axi 4.3%
7 projf-explore 3.3%
8 scr1 3.2%
9 pulpissimo 3.0%
10 eurorack-pmod 3.0%
11 ibex 2.6%
12 opentitan 2.2%
13 hdmi 2.1%
14 cv32e40p 2.0%
15 NES_MiSTer 1.8%
16 Cores-VeeR-EH2 1.5%
17 rsd 1.1%
18 bsg_manycore 0.9%
19 lowrisc-chip 0.8%
20 Cores-VeeR-EH1 0.0%

Did you konow that SystemVerilog is
the 89th most popular programming language
based on number of metions?