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Basejump_stl Alternatives
Similar projects and alternatives to basejump_stl
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PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
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satcat5
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
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axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better basejump_stl alternative or higher similarity.
basejump_stl discussion
basejump_stl reviews and mentions
Posts with mentions or reviews of basejump_stl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-01-20.
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Extra-wide aspect ratio FIFO in Vivado?
BaseJump STL ( https://github.com/bespoke-silicon-group/basejump_stl ) has lots of these plumbing modules, silicon-validated several times
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Cross module reference (XMR)?
It depends on your mapping algorithm and whether the tools you’re looking at supported mixed-language synthesis, but you can always use our battle-tested components for these kind of functions: https://github.com/bespoke-silicon-group/basejump_stl
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Any recommendations for an RTL "standard library"?
https://github.com/bespoke-silicon-group/basejump_stl maybe?
- Data flow ternary vs behavioral case statements
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Stats
Basic basejump_stl repo stats
4
559
9.3
6 days ago
bespoke-silicon-group/basejump_stl is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of basejump_stl is SystemVerilog.
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