Basejump_stl Alternatives

Similar projects and alternatives to basejump_stl

• chisel

  1 3,281 9.6 Scala basejump_stl VS chisel

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

• opentitan

  1 2,025 9.9 SystemVerilog basejump_stl VS opentitan

  OpenTitan: Open source silicon root of trust

  

• InfluxDB

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• surf

  1 257 0.0 VHDL basejump_stl VS surf

  A huge VHDL library for FPGA development (by slaclab)

  

• fusesoc

  1 1,042 7.6 Python basejump_stl VS fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

• PipelineC

  1 500 0.0 Python basejump_stl VS PipelineC

  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

• satcat5

  1 240 0.0 VHDL basejump_stl VS satcat5

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

• tiny-cores

  1 9 10.0 Verilog basejump_stl VS tiny-cores

  Collection of assorted small cores

  

• Onboard AI

  getonboard.dev

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• axi

  1 817 0.0 SystemVerilog basejump_stl VS axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• fusesoc-cores

  1 92 0.0 basejump_stl VS fusesoc-cores

  FuseSoC standard core library