Top 5 SystemVerilog Asic Projects

• axi

  3 933 6.1 SystemVerilog

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• cheshire

  1 107 7.6 SystemVerilog

  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• libsv

  2 19 3.6 SystemVerilog

  An open source, parameterized SystemVerilog digital hardware IP library

• ApogeoRV

  1 13 9.3 SystemVerilog

  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

• rp32

  3 8 5.9 SystemVerilog

  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

Project mention: How to design a more elegant and simple instraction decoder | /r/RISCV | 2023-05-24

Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv

• SaaSHub

  www.saashub.com featured

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

SystemVerilog Asic related posts

• How to design a more elegant and simple instraction decoder

  1 project | /r/RISCV | 24 May 2023

• 432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space

  3 projects | /r/RISCV | 9 May 2023

• The CORE-V CVA6 is a RISC-V CPU capable of booting Linux

  1 project | news.ycombinator.com | 23 Oct 2022

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