ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions. (by GabbedT)

ApogeoRV Alternatives

Similar projects and alternatives to ApogeoRV based on common topics and language

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better ApogeoRV alternative or higher similarity.

ApogeoRV reviews and mentions

Posts with mentions or reviews of ApogeoRV. We have used some of these posts to build our list of alternatives and similar projects.
  • Need help with B.tech last year project! On cache memory controller design using verilog hdl
    1 project | /r/chipdesign | 19 Jan 2023
    I am designing a cache controller in SystemVerilog for my RISCV CPU, it's currently under verification so there are a lot of bugs, but you can take a look to the code (https://github.com/GabbedT/RV32-Apogeo/tree/main/Hardware/Memory%20System/Data%20Cache) and to the documentation (https://github.com/GabbedT/RV32-Apogeo/blob/main/Docs/data-cache.md) (not up to date). Take this just as an example because I'm simply a third year bachelor student and this is only a personal project (I'm not followed by a professor or anything like that) so it might not be the best way to implement a cache controller.

Stats

Basic ApogeoRV repo stats
1
13
9.3
about 1 month ago

GabbedT/ApogeoRV is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of ApogeoRV is SystemVerilog.


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