Need help with B.tech last year project! On cache memory controller design using verilog hdl

• ApogeoRV

  1 13 9.3 SystemVerilog

  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

I am designing a cache controller in SystemVerilog for my RISCV CPU, it's currently under verification so there are a lot of bugs, but you can take a look to the code (https://github.com/GabbedT/RV32-Apogeo/tree/main/Hardware/Memory%20System/Data%20Cache) and to the documentation (https://github.com/GabbedT/RV32-Apogeo/blob/main/Docs/data-cache.md) (not up to date). Take this just as an example because I'm simply a third year bachelor student and this is only a personal project (I'm not followed by a professor or anything like that) so it might not be the best way to implement a cache controller.

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