- Arm IPO to kick off today with company valued at $54.5B
- What’s the Smallest Variety of CHERI? (2022)
- Hot Chips 2023: SiFive’s P870 Takes RISC-V Further
- Basic UART implementation in UART
- Design and Rationale of the RISC-V Composable Custom Extensions Specification [video]
- Verilator - Do I need to maintain two testbench suits?
- agg23/fpga-gameandwatch: Game and Watch for Analogue Pocket and MiSTer
- Interpreter on an FPGA?
- Putting out the hardware dumpster fire
- Looking to work in Open Source Silicon and RISC-V? lowRISC is hiring DV and infrastructure engineers
- They just pirated my open source 8088 BIOS
- building pulpissimo
- C++ Verification Testbench Best-Practice Resources?
- Best fpga for begginers
- CPU Design Verification Interview
- How to use verilator to transfer a design with multiple files to a verilated model?
- SDRAM/DDR
- Help with a SPI protocol using verilog!!
- How to design a more elegant and simple instraction decoder
- How hard would it be to write fractional 0-1 informational states in different media off the shelf (RAM, HDD, SSD, etc? And w/ controller hacks allowed?)
- 432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
- Best tutorial on DDR protocol
- 432-Core RISC-V European Processor Designed for Use in Space Taped Out
- Cpu project
- Show HN: Tamagotchi P1 for FPGAs
- Ushering In a New Era for Open-Source Silicon Development (CEO of lowrisc , a non profit that develops open source hardware on why open source hardware failed in the past, and how lowrisc does things differently)
- Tamagotchi for FPGA
- Atari 800XL Remake
- What is to be gained from ISA convergence on all levels of computing?
- verilog-ext: Verilog Extensions for Emacs
- How to read and write data from SD card?
- SPI master driver for spi slave
- SPI master driver for spi slave
- FPGA - DS3231 interface
- I want to learn to interface HDMI to Xilinx Kintex 7 FPGA. Can you please provide any resources? I don't have prior experience in interfacing HDMI.
- I attempted to design an FIR FILTER in systemverilog. It has a changeable coefficients with a update signal. I’d love your comments reviewing mine, and suggestions to improve.
- Ending this debate once and for all.
- How can "worst negative slack" become _worse_ when I *lower* the clock?
- Need help with B.tech last year project! On cache memory controller design using verilog hdl
- A simple high-throughput open-source packet generator
- Xilinx xsim is BLAZINGLY FAST. Xsim dumping all signals 5x faster than Icarus Verilog dumping no signals!
- My first CPU on FPGA
- Help with Castlevania 3 (NES) on MiSTer
- Which FPGA for getting into RISC-V?
- My first FSM in FPGA
- Potential Solution to FPGA Shortage
- The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
- Xilinx alternatives??
- Phoronix: "AMD, Google, Microsoft & NVIDIA Announce "Caliptra" Open-Source Root of Trust"
- Simon Peyton Jones – Haskell Foundation Podcast