Top 3 SystemVerilog Hdl Projects
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BrianHG-DDR3-Controller
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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ApogeoRV
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
SystemVerilog Hdl related posts
Index
What are some of the best open-source Hdl projects in SystemVerilog? This list will help you:
| Project | Stars | |
|---|---|---|
| 1 | BrianHG-DDR3-Controller | 60 |
| 2 | libsv | 19 |
| 3 | ApogeoRV | 13 |
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