Top 13 SystemVerilog Systemverilog Projects

hdmi

7 1,004 4.7 SystemVerilog

Send video/audio over HDMI on an FPGA

Project mention: HDMI Forum Rejects Open-Source HDMI 2.1 Driver Support Sought by AMD | news.ycombinator.com | 2024-02-28

Relevant caveat from its readme: https://github.com/hdl-util/hdmi?tab=readme-ov-file#hdmi-ado...

axi

3 920 6.8 SystemVerilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
cheshire

1 102 7.8 SystemVerilog

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

Project mention: Cpu project | /r/RISCV | 2023-05-08

If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here

BrianHG-DDR3-Controller

2 60 10.0 SystemVerilog

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
libsv

2 19 3.6 SystemVerilog

An open source, parameterized SystemVerilog digital hardware IP library
risc-v-single-cycle

1 16 10.0 SystemVerilog

A Single Cycle Risc-V 32 bit CPU
ApogeoRV

1 13 9.3 SystemVerilog

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
mips_cpu

1 10 10.0 SystemVerilog

Single Cycle 32 bit MIPS
rggen-sv-rtl

1 10 4.7 SystemVerilog

Common SystemVerilog RTL modules for RgGen
rp32

3 8 5.9 SystemVerilog

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

Project mention: How to design a more elegant and simple instraction decoder | /r/RISCV | 2023-05-24

Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv

Arithmetic-Circuits

1 3 3.8 SystemVerilog

This repository contains different modules which execute arithmetic operations. (by GabbedT)
TCB

1 1 8.2 SystemVerilog

Tightly Coupled Bus, low complexity, high performance system bus.
basys3_fpga_sandbox

1 0 10.0 SystemVerilog

Learning the basics of Systemverilog, testbench and more.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

SystemVerilog Systemverilog related posts

How to design a more elegant and simple instraction decoder
1 project | /r/RISCV | 24 May 2023
Is there a completely free computer?
1 project | /r/linux | 3 Oct 2022
Skid Buffer
1 project | /r/FPGA | 23 Jul 2022

Index

What are some of the best open-source Systemverilog projects in SystemVerilog? This list will help you:

	Project	Stars
1	hdmi	1,004
2	axi	920
3	cheshire	102
4	BrianHG-DDR3-Controller	60
5	libsv	19
6	risc-v-single-cycle	16
7	ApogeoRV	13
8	mips_cpu	10
9	rggen-sv-rtl	10
10	rp32	8
11	Arithmetic-Circuits	3
12	TCB	1
13	basys3_fpga_sandbox	0