SystemVerilog Cpu Projects
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting LinuxProject mention: Recommendations for RISC-V on FPGA | /r/FPGA | 2023-03-08
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
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Which FPGA for getting into RISC-V?
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The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
1 project | news.ycombinator.com | 23 Oct 2022