SystemVerilog Cpu

Open-source SystemVerilog projects categorized as Cpu
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Topics: #risc-v #Asic #Fpga #systemverilog-hdl #rv64gc
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SystemVerilog Cpu Projects

  • cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Project mention: Recommendations for RISC-V on FPGA | /r/FPGA | 2023-03-08

    Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-03-08.

SystemVerilog Cpu related posts

Index

Project Stars
1 cva6 1,829

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Updating dependencies is time-consuming.
Solutions like Dependabot or Renovate update but don't merge dependencies. You need to do it manually while it could be fully automated! Add a Merge Queue to your workflow and stop caring about PR management & merging. Try Mergify for free.
blog.mergify.com