rp32

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle). (by jeras)

Rp32 Alternatives

Similar projects and alternatives to rp32

  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  • ibex

    20 rp32 VS ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

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  • Cores-VeeR-EH1

    8 rp32 VS Cores-VeeR-EH1

    VeeR EH1 core

  • simple-riscv

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  • cheshire

    1 rp32 VS cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  • friscv

    RISCV CPU implementation in SystemVerilog

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  • ApogeoRV

    1 rp32 VS ApogeoRV

    A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better rp32 alternative or higher similarity.

rp32 reviews and mentions

Posts with mentions or reviews of rp32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-30.

Stats

Basic rp32 repo stats
3
8
5.9
7 months ago

jeras/rp32 is an open source project licensed under Apache License 2.0 which is an OSI approved license.

The primary programming language of rp32 is SystemVerilog.


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