friscv

RISCV CPU implementation in SystemVerilog (by dpretet)
Review riscv-cpu Riscv Rv32i Verilog Systemverilog Fpga Asic risc-v Assembler fpga-soc asic-design Axi4 axi4-protocol crossbar
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Friscv Alternatives

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dpretet
friscv

  1. scr1

    2 friscv VS scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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  3. darkriscv

    4 friscv VS darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  4. rp32

    3 friscv VS rp32

    RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

  5. fpga_riscv_cpu

    1 friscv VS fpga_riscv_cpu

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  6. ravenoc

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    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

  7. cheshire

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  8. cv32e40p

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    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

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  10. airisc_core_complex

    1 friscv VS airisc_core_complex

    Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

  11. Cores-VeeR-EH1

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  12. jtag_uart_example

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  13. cgra4ml

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    An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

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4.7
6 months ago

dpretet/friscv is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of friscv is SystemVerilog.

Popular Comparisons

  1. friscv VS scr1
  2. friscv VS darkriscv
  3. friscv VS rp32
  4. friscv VS fpga_riscv_cpu
  5. friscv VS ravenoc
  6. friscv VS cheshire
  7. friscv VS cv32e40p
  8. friscv VS airisc_core_complex
  9. friscv VS Cores-VeeR-EH1
  10. friscv VS cgra4ml

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Did you know that SystemVerilog is
the 98th most popular programming language
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