rp32
ApogeoRV
| rp32 | ApogeoRV | |
|---|---|---|
| 3 | 1 | |
| 8 | 13 | |
| - | - | |
| 5.9 | 9.3 | |
| 8 months ago | about 2 months ago | |
| SystemVerilog | SystemVerilog | |
| Apache License 2.0 | MIT License |
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rp32
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How to design a more elegant and simple instraction decoder
Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv
- Mapping compressed 'C' instructions to their 32b counterparts.
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Is a single cycle CPU of any use besides learning?
I am writing a RISC-V core with a strict IPC=1 (instructions per cycle). One piece is still in my mind, but the CPU is already passing instruction set tests.https://github.com/jeras/rp32The code was not properly synthesized yet, and there is almost no documentation, if you wish to use anything, but do not know how to, you can ask for help as a GitHub issue. But I do not know how much time I will have to answer.
ApogeoRV
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Need help with B.tech last year project! On cache memory controller design using verilog hdl
I am designing a cache controller in SystemVerilog for my RISCV CPU, it's currently under verification so there are a lot of bugs, but you can take a look to the code (https://github.com/GabbedT/RV32-Apogeo/tree/main/Hardware/Memory%20System/Data%20Cache) and to the documentation (https://github.com/GabbedT/RV32-Apogeo/blob/main/Docs/data-cache.md) (not up to date). Take this just as an example because I'm simply a third year bachelor student and this is only a personal project (I'm not followed by a professor or anything like that) so it might not be the best way to implement a cache controller.
What are some alternatives?
riscv-formal - RISC-V Formal Verification Framework
KinnowCPU - CPU implementing the Limn2600 architecture.
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
friscv - RISCV CPU implementation in SystemVerilog
riscv - RISC-V CPU Core (RV32IM)
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Cores-VeeR-EH1 - VeeR EH1 core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
simple-riscv - A simple three-stage RISC-V CPU