rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle). (by jeras)
simple-riscv
A simple three-stage RISC-V CPU (by hamsternz)
| rp32 | simple-riscv | |
|---|---|---|
| 3 | 5 | |
| 8 | 19 | |
| - | - | |
| 5.9 | 2.7 | |
| 8 months ago | about 3 years ago | |
| SystemVerilog | VHDL | |
| Apache License 2.0 | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rp32
Posts with mentions or reviews of rp32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-30.
-
How to design a more elegant and simple instraction decoder
Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv
- Mapping compressed 'C' instructions to their 32b counterparts.
-
Is a single cycle CPU of any use besides learning?
I am writing a RISC-V core with a strict IPC=1 (instructions per cycle). One piece is still in my mind, but the CPU is already passing instruction set tests.https://github.com/jeras/rp32The code was not properly synthesized yet, and there is almost no documentation, if you wish to use anything, but do not know how to, you can ask for help as a GitHub issue. But I do not know how much time I will have to answer.
simple-riscv
Posts with mentions or reviews of simple-riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-23.
-
How to run DOOM on a custom-made CPU in VHDL
Have a look at https://github.com/hamsternz/simple-riscv/tree/main/sw for how I did this for my toy processor. In particular https://github.com/hamsternz/simple-riscv/tree/main/sw/image_to_mem does the heavy lifting.
- Running VIVADO project from batch- linux , by using tcl file.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
-
Is a single cycle CPU of any use besides learning?
If you want to see my ISA testing source have a look at: https://github.com/hamsternz/simple-riscv/blob/main/sw/asm/isa_test.S
What are some alternatives?
When comparing rp32 and simple-riscv you can also consider the following projects:
riscv-formal - RISC-V Formal Verification Framework
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
riscv-tests
friscv - RISCV CPU implementation in SystemVerilog
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Cores-VeeR-EH1 - VeeR EH1 core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
ApogeoRV - A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.