Top 23 VHDL Vhdl Projects

• ghdl

  26 2,206 9.8 VHDL

  VHDL 2008/93/87 simulator

  

• vunit

  10 681 8.3 VHDL

  VUnit is a unit testing framework for VHDL/SystemVerilog

  

• InfluxDB

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• bladeRF-wiphy

  2 363 0.0 VHDL

  bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

  

• forth-cpu

  2 315 2.6 VHDL

  A Forth CPU and System on a Chip, based on the J1, written in VHDL

• rust_hdl

  8 298 9.3 VHDL
  

Project mention: How to configure vim like an IDE | /r/vim | 2023-06-27

rust_hdl

• surf

  1 284 8.9 VHDL

  A huge VHDL library for FPGA development (by slaclab)

  

• potato

  1 245 0.0 VHDL

  A simple RISC-V processor for use in FPGA designs. (by skordal)

• WorkOS

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• spi-fpga

  2 157 0.0 VHDL

  SPI master and SPI slave for FPGA written in VHDL

• neoTRNG

  10 152 7.5 VHDL

  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06

• w11

  1 116 4.6 VHDL

  PDP-11/70 CPU core and SoC

• bit-serial

  1 109 6.7 VHDL

  A bit-serial CPU written in VHDL, with a simulator written in C.

Project mention: The ancient world before computers had stacks or heaps | news.ycombinator.com | 2024-04-03

I wrote a Forth interpreter for a SUBLEQ machine (https://github.com/howerj/subleq), and for a bit-serial machine (https://github.com/howerj/bit-serial), both of which do not have a function call stack which is a requirement of Forth. SUBLEQ also does not allow indirect loading and stores as well and requires self-modifying code to do anything non-trivial. The approach I took for both machines was to build a virtual machine that could do those things, along with cooperative multithreading. The heap, if required, is written in Forth, along with a floating point word-set (various MCUs not having instructions for floating point numbers is still fairly common, and can be implemented as calls to software functions that implement them instead).

I would imagine that other compilers took a similar approach which wasn't mentioned.

• AXI4

  4 101 7.5 VHDL

  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

  

• dvb_fpga

  2 96 2.2 VHDL

  RTL implementation of components for DVB-S2

  

• fpga-fft

  1 87 0.0 VHDL

  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

  

• uart-for-fpga

  1 84 0.0 VHDL

  Simple UART controller for FPGA written in VHDL

• neorv32-setups

  5 52 8.7 VHDL

  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03

Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.

• fpu

  1 46 6.1 VHDL

  IEEE 754 floating point library in system-verilog and vhdl (by taneroksuz)

• VHDL-Guide

  2 34 1.8 VHDL

  VHDL Guide

• spi-to-axi-bridge

  1 31 0.0 VHDL

  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

  

• Compliance-Tests

  1 25 4.8 VHDL

  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

  

• karabas-128

  1 23 0.0 VHDL

  Karabas-128. ZX Spectrum 128k clone, based on CPLD Altera EPM7128STC100

• ndk-app-minimal

  4 23 8.2 VHDL

  Minimal Application based on Network Development Kit (NDK) for FPGA cards

  

• fpu-sp

  3 20 6.9 VHDL

  IEEE 754 floating point library in system-verilog and vhdl

Project mention: Intel discontinues Nios II IP | /r/FPGA | 2023-06-14

My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.

• SaaSHub

  www.saashub.com sponsored

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VHDL Vhdl related posts

• A really tiny and platform-independent true random number generator for FPGAs and ASICs
  1 project | /r/cryptography | 6 Nov 2023
• A really tiny and platform-independent true random number generator for FPGAs and ASICs
  1 project | /r/VHDL | 6 Nov 2023
• A really tiny and platform-independent true random number generator for FPGAs and ASICs
  1 project | /r/FPGA | 6 Nov 2023
• Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
  1 project | news.ycombinator.com | 4 Nov 2023
• Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
  1 project | news.ycombinator.com | 4 Nov 2023
• An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
  1 project | /r/RISCV | 24 Jul 2023
• Intel discontinues Nios II IP
  3 projects | /r/FPGA | 14 Jun 2023
• A note from our sponsor - WorkOS
  workos.com | 26 Apr 2024

  The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning. Learn more →

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