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Mentions Stars Project Description
6 299 A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
3 73 GBA for MiSTer
2 113 OpenXenium - Open Source Xenium Modchip CPLD replacement project for the Original Xbox
2 7 WonderSwan Color for MiSTer
2 6 Hardware implementation of Saber
1 1,349 VHDL 2008/93/87 simulator
1 458 VUnit is a unit testing framework for VHDL/SystemVerilog
1 399 GameCube Digital AV converter
1 362 Core sources and tools for the MIST board
1 205 UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC โ€“ resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
1 26 FPGA optimized RISC-V (RV32IM) implemenation
1 23
1 16 SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
1 9 CNN-to-FPGA-framework for small CNN, written in VHDL and Python
1 5 VHDL RISC-V JTAG debug transport module (DTM) - compatible to the RISC-V debug specification
1 5 UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform
1 3 Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
1 1 LTC2324-16 driver for Xilinx AXI-DMA

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