VHDL Asic

Open-source VHDL projects categorized as Asic
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Topics: Fpga Vhdl Random Firmware Python
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Top 3 VHDL Asic Projects

  • vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

  • surf

    A huge VHDL library for FPGA development (by slaclab)

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • neoTRNG

    🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

    • Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

VHDL Asic related posts

Index

What are some of the best open-source Asic projects in VHDL? This list will help you:

Project Stars
1 vunit 682
2 surf 285
3 neoTRNG 152

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