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Top 23 VHDL Fpga Projects
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neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
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PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Project mention: PipelineC Example: FM Radio Demodulation (FPGA SDR) | news.ycombinator.com | 2024-03-03Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
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vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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catapult-v3-smartnic-re
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
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neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
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fpu
IEEE 754 single and double precision floating point library in systemverilog and vhdl (by taneroksuz)
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neoapple2
Port of Stephen A. Edwards's Apple2fpga to PYNQ-Z1 (Xilinx Zynq FPGA), to emulate an Apple II+.
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VHDL Fpga discussion
VHDL Fpga related posts
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A really tiny and platform-independent true random number generator for FPGAs and ASICs
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A really tiny and platform-independent true random number generator for FPGAs and ASICs
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A really tiny and platform-independent true random number generator for FPGAs and ASICs
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Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
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Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
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An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
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www.saashub.com | 5 Dec 2024
Index
What are some of the best open-source Fpga projects in VHDL? This list will help you:
Project | Stars | |
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1 | neorv32 | 1,619 |
2 | vunit | 745 |
3 | PipelineC | 605 |
4 | vscode-terosHDL | 574 |
5 | openfpga-SNES | 388 |
6 | surf | 349 |
7 | forth-cpu | 334 |
8 | Hastlayer-SDK | 302 |
9 | neoTRNG | 173 |
10 | spi-fpga | 166 |
11 | w11 | 119 |
12 | catapult-v3-smartnic-re | 116 |
13 | sdram-fpga | 115 |
14 | dvb_fpga | 111 |
15 | fpga-fft | 106 |
16 | uart-for-fpga | 91 |
17 | neorv32-setups | 64 |
18 | fpu | 60 |
19 | boxlambda | 45 |
20 | neoapple2 | 43 |
21 | my-discrete-fpga | 40 |
22 | Compliance-Tests | 29 |
23 | ndk-fpga | 29 |