vunit

VUnit is a unit testing framework for VHDL/SystemVerilog (by VUnit)

Vunit Alternatives

Similar projects and alternatives to vunit

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better vunit alternative or higher similarity.

vunit reviews and mentions

Posts with mentions or reviews of vunit. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-11.
  • Software languages vs HDLs for verification
    3 projects | /r/FPGA | 11 Feb 2023
    My goto tools for verification in VHDL are UVVM and VUnit
  • Libero - Inefficient Simulations
    1 project | /r/FPGA | 29 Jan 2023
    I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
  • Books About Testing and Verification
    2 projects | /r/FPGA | 25 Jan 2023
    I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
  • A couple of questions for the experts
    2 projects | /r/FPGA | 22 Dec 2022
  • Reference of verification IPs
    7 projects | /r/FPGA | 2 Nov 2022
    Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
  • SystemVerilog testbench library
    1 project | /r/FPGA | 14 Sep 2022
    I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
  • The Vivado 2021.2 is out thread
    1 project | /r/FPGA | 9 Nov 2021
    As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
  • How do you do automated testing of your HDL?
    1 project | /r/FPGA | 16 Jun 2021
  • VHDL Testbench Library Comparison
    2 projects | /r/FPGA | 8 Apr 2021
    Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
  • The simplest way to automate my testbench?
    1 project | /r/FPGA | 21 Jan 2021
    I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/
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Stats

Basic vunit repo stats
10
681
8.3
23 days ago

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