Converting VHDL to Verilog using GHDL

• ghdl

  26 2,218 9.8 VHDL

  VHDL 2008/93/87 simulator

  

Try a question here: https://github.com/ghdl/ghdl/issues . I have only used GHDL for VHDL, and it worked well for what I was doing with it, but the creator/chief maintainer(?) (Tristan Gingold) should be able to set your issue straight in a short while, and he is pretty active on github.

• neorv32-verilog

  5 40 8.1 Verilog

  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog

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