neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (by stnolting)

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neorv32-verilog reviews and mentions

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Stats

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5
39
8.1
6 days ago

stnolting/neorv32-verilog is an open source project licensed under BSD 3-clause "New" or "Revised" License which is an OSI approved license.

The primary programming language of neorv32-verilog is Verilog.


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