Verilog Asic

Open-source Verilog projects categorized as Asic

Top 9 Verilog Asic Projects

  • serv

    SERV - The SErial RISC-V CPU

    Project mention: RISC-V support in Android just got a big setback | news.ycombinator.com | 2024-04-30

    > Right now, most devices on the market do not support the C extension

    This is not true and easily verifiable.

    The C extension is defacto required, the only cores that don't support it are special purpose soft cores.

    C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file

    Supports M and C extensions https://github.com/YosysHQ/picorv32

    Another sized optimized core with C extension support https://github.com/lowrisc/ibex

    C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html

    This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax

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  • riscv

    RISC-V CPU Core (RV32IM)

    Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

    I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

  • biriscv

    32-bit Superscalar RISC-V CPU

  • open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  • tiny-asic-1_58bit-matrix-mul

    Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

    Project mention: Tiny ASIC for BitNet (1.58B / ternary) | news.ycombinator.com | 2024-06-27
  • airisc_core_complex

    Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

    SaaSHub logo
  • neorv32-verilog

    ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

  • ITA-CORES

    RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

    Project mention: SoC RISC-V: An ASIC Implementation of the FEMTORV32 | news.ycombinator.com | 2023-12-20
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Verilog Asic related posts

  • SERV – The SErial RISC-V CPU

    1 project | news.ycombinator.com | 10 Dec 2023
  • SERV: A bit-serial RISC-V core

    1 project | news.ycombinator.com | 28 Jun 2023
  • SERV – open-source Tiny SErial RISC-V CPU

    1 project | news.ycombinator.com | 14 Jun 2023
  • [D][P] Represent Analog Circuits as Graphs

    3 projects | /r/MachineLearning | 15 Apr 2023
  • how small team survive from cadence cost

    1 project | /r/chipdesign | 15 Jan 2023
  • Minimax: a Compressed-First, Microcoded RISC-V CPU

    4 projects | /r/FPGA | 26 Oct 2022
  • Apple to Move a Part of Its Embedded Cores to RISC-V

    4 projects | news.ycombinator.com | 16 Sep 2022
  • A note from our sponsor - InfluxDB
    www.influxdata.com | 22 Jul 2024
    Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality. Learn more →

Index

What are some of the best open-source Asic projects in Verilog? This list will help you:

Project Stars
1 serv 1,336
2 riscv 1,123
3 biriscv 790
4 open-register-design-tool 186
5 cheshire 159
6 tiny-asic-1_58bit-matrix-mul 94
7 airisc_core_complex 80
8 neorv32-verilog 47
9 ITA-CORES 37

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