Top 6 Verilog Asic Projects

serv

4 1,087 0.0 Verilog

SERV - The SErial RISC-V CPU

Project mention: SERV: A bit-serial RISC-V core | news.ycombinator.com | 2023-06-28
riscv

1 902 1.8 Verilog

RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
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biriscv

2 644 0.0 Verilog

32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21
livehd

0 183 0.0 Verilog

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
open-register-design-tool

0 172 0.0 Verilog

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
neorv32-verilog

2 28 10.0 Verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Project mention: Converting VHDL to Verilog using GHDL | /r/VHDL | 2022-10-10

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-04.