Verilog Asic

Open-source Verilog projects categorized as Asic

Top 6 Verilog Asic Projects

  • serv

    SERV - The SErial RISC-V CPU

    Project mention: SERV: A bit-serial RISC-V core | | 2023-06-28
  • riscv

    RISC-V CPU Core (RV32IM)

    Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

    I have been trying to execute some instructions to the ultraembedded riscv module

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  • biriscv

    32-bit Superscalar RISC-V CPU

    Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21
  • livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  • open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • neorv32-verilog

    ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

    Project mention: Converting VHDL to Verilog using GHDL | /r/VHDL | 2022-10-10
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-04.

Verilog Asic related posts


What are some of the best open-source Asic projects in Verilog? This list will help you:

Project Stars
1 serv 1,087
2 riscv 902
3 biriscv 644
4 livehd 183
5 open-register-design-tool 172
6 neorv32-verilog 28
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