♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Why do you think that https://github.com/ultraembedded/biriscv is a good alternative to neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Why do you think that https://github.com/ultraembedded/biriscv is a good alternative to neorv32-verilog