neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (by stnolting)
edalize
An abstraction library for interfacing EDA tools (by olofk)
| neorv32-verilog | edalize | |
|---|---|---|
| 5 | 4 | |
| 40 | 593 | |
| - | - | |
| 8.1 | 7.2 | |
| 6 days ago | 2 days ago | |
| Verilog | Python | |
| BSD 3-clause "New" or "Revised" License | BSD 2-clause "Simplified" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32-verilog
Posts with mentions or reviews of neorv32-verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-10.
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Converting VHDL to Verilog using GHDL
I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog
- Convert VHDL to Verilog using GHDL (using a RISC-V core as example)
- Show HN: Convert VHDL to Verilog using GHDL (+ first evaluation)
edalize
Posts with mentions or reviews of edalize.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-06.
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
When comparing neorv32-verilog and edalize you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
riscv - RISC-V CPU Core (RV32IM)
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
serv - SERV - The SErial RISC-V CPU
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
ghdl - VHDL 2008/93/87 simulator
apio - :seedling: Open source ecosystem for open FPGA boards
naja - Structural Netlist API (and more) for EDA post synthesis flow development
icestudio - :snowflake: Visual editor for open FPGA boards
rggen - Code generation tool for control and status registers
sphinx-vhdl