edalize
skywater-pdk
Our great sponsors
edalize | skywater-pdk | |
---|---|---|
4 | 27 | |
579 | 2,806 | |
- | 2.2% | |
7.3 | 2.3 | |
21 days ago | 7 months ago | |
Python | Python | |
BSD 2-clause "Simplified" License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
edalize
-
Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
-
Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
skywater-pdk
-
Libre Silicon – Free semiconductors for everyone
It looks neat, but the process node is 1 um with 3 metal layers.
The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)
-
DIY-Thermocam: The Affordable and Easy-to-Build Thermal Camera for Everyone
That would be really neat, but I haven't seen anyone even make a CMOS imager on SKY130.
https://github.com/google/skywater-pdk
One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7.
https://www.digikey.com/en/products/detail/excelitas-technol...
One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it.
https://www.digikey.com/en/products/detail/panasonic-electro...
https://github.com/IdleHandsProject/diycamera (digiOBSCURA)
One could experiment with microbolometers on tinytapeout. https://elicit.org/search?q=cmos+microbolometer
-
Making open source hardware design a reality
Taping out an actual chip inevitably involves IP that's not yours, e.g. the standard cell library and other 'physical' IP like memories and flash. You cannot open source that as it is not yours and in general the owners of it won't want to open source it either (though there are exceptions e.g. the Skywater 130nm PDK https://github.com/google/skywater-pdk).
In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).
- Compiling Code into Silicon
-
Open cores, ISAs, etc.: what is open about them?
"As should be obvious by now, there is no situation where these foundry processes and tools are open source."
This is already false. The famous OpenPDK by Skywater (sponsored by Google) is proving this article wrong from the beginning. (https://github.com/google/skywater-pdk)
Yes, thats a rather old technology node, but you can now synthesize your free RISC-V design with a free Toolchain (openROAD) onto this open PDK.
Amazing times!
So I would say to that extent they do, the foundries provide dev kits with cells to use on their process, and there's definitely the same incentive, good reusable IP gets you products faster which gets them more business. I think a lot of the landscape is just driven by the sheer cost of getting it wrong. Spinning a pcb is a bummer. Needing a new mask set is so much worse.
There is eFabless, among other efforts in the vein you describe, they do a multi project wafer shuttle thing that google sponsors using skywater. It's supposedly an open source PDK, I haven't used it.
-
Kickstarting IC design
Skywater Technology is a semiconductor manufacturing company which has made its 130nm CMOS process node and its standard cells open-source (due to the efforts of Google, yes, you heard it right- Google.) https://github.com/google/skywater-pdk
-
"file extensions are hints as to what might be in the file, not a standard."
Regarding Integrated Circuit, I was very happy, when skywater-pdk, that started the OpenSilicon Era, you can submit your design and get it produced in a 130nm tecnology for free(in you get selected),as long is full open, 130nm is a hold node, but still you can do amazing thing with it, expecially, analog one, Example of First Run Project
-
How are modern processors and their architecture designed?
You always need a description of the actual silicon used for the RTL-to-GDS flow. This is the PDK. Currently there is AFAIK only one open source PDK available, typically companies are very strict about giving information to third parties. But the Skywater 130nm PDK really gives you a chance to look into, and freely work and design ICs with it: https://github.com/google/skywater-pdk
-
Nano full node on Mac M1
That's an easier thing for me to sell than try to ask for a development contract to spend my time porting Nano to M1, or for me to raise enough money to fabricate open-source silicon so I can sell a computer that comes with the source code to the processor ( see https://github.com/google/skywater-pdk and https://github.com/efabless/openlane ). FYI, it would take somewhere between 100,000 and 250,000 Nano to run a full wafer at Skywater, so if someone is really serious about being able to educate node operators on how the silicon their node depends on is built, let's figure out how to get this done.
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
RocksDB - A library that provides an embeddable, persistent key-value store for fast storage.
gssi - Stuff I worked on while at GSSI (L'Aquila, Italy)
quibble - Quibble - the custom Windows bootloader
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
Verilog.jl - Verilog for Julia
chisel - Chisel: A Modern Hardware Design Language
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
PeakRDL-ipxact - Import and export IP-XACT XML register models
apio - :seedling: Open source ecosystem for open FPGA boards
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU