Python Verilog

Open-source Python projects categorized as Verilog
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Vhdl Python Rtl Systemverilog Hdl
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Top 11 Python Verilog Projects

Verilog

  1. cocotb

    cocotb: Python-based chip (RTL) verification

    Project mention: Use cocotb to test and verify chip designs in Python | news.ycombinator.com | 2024-11-22

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  3. openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  4. fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

  5. edalize

    An abstraction library for interfacing EDA tools

  6. pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

  7. hdl_checker

    Repurposing existing HDL tools to help writing better code

  8. cocotb-bus

    Pre-packaged testbenching tools and reusable bus interfaces for cocotb

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  10. sphinxcontrib-hdl-diagrams

    Sphinx Extension which generates various types of diagrams from Verilog code.

  11. vcdvcd

    Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

  12. PyChip-py-hcl

    A Hardware Construct Language

  13. eda-log-file-warning-suppressor

    Suppresses warnings in EDA logfiles.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Python Verilog related posts

  • Use cocotb to test and verify chip designs in Python

    1 project | news.ycombinator.com | 22 Nov 2024

  • Designing a Low Latency 10G Ethernet Core

    2 projects | /r/FPGA | 4 Jul 2023

  • Interactive Chess on Factorio CPU

    9 projects | /r/factorio | 5 May 2023

  • Introducing CoHDL

    5 projects | /r/FPGA | 15 Apr 2023

  • How is Python used in test automation in embedded systems?

    2 projects | /r/embedded | 19 Apr 2023

  • Use cocotb to test and verify chip designs in Python

    1 project | /r/cocotb | 12 Apr 2023

  • Trying to learn and work with FPGAs

    4 projects | /r/FPGA | 12 Apr 2023
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Index

What are some of the best open-source Verilog projects in Python? This list will help you:

# Project Stars
1 cocotb 1,948
2 openlane 1,465
3 fusesoc 1,267
4 edalize 681
5 pymtl3 409
6 hdl_checker 207
7 cocotb-bus 65
8 sphinxcontrib-hdl-diagrams 59
9 vcdvcd 58
10 PyChip-py-hcl 43
11 eda-log-file-warning-suppressor 2

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