Python Verilog

Open-source Python projects categorized as Verilog

Top 13 Python Verilog Projects

  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    Project mention: Designing a Low Latency 10G Ethernet Core | /r/FPGA | 2023-07-04

    The use of cocotb and pyuvm for verification

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Project mention: [D][P] Represent Analog Circuits as Graphs | /r/MachineLearning | 2023-04-15

    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.

  • WorkOS

    The modern API for authentication & user identity. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

  • edalize

    An abstraction library for interfacing EDA tools

  • pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

    Project mention: Firrtl – Flexible Intermediate Representation for RTL | | 2023-07-15
  • hdl_checker

    Repurposing existing HDL tools to help writing better code

  • vcdvcd

    Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.


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  • sphinxcontrib-hdl-diagrams

    Sphinx Extension which generates various types of diagrams from Verilog code.

  • cocotb-bus

    Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  • PyChip-py-hcl

    A Hardware Construct Language

  • deepsocflow

    An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

  • teroshdl-documenter-demo

    This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

  • eda-log-file-warning-suppressor

    Suppresses warnings in EDA logfiles.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-07-15.

Python Verilog related posts


What are some of the best open-source Verilog projects in Python? This list will help you:

Project Stars
1 cocotb 1,526
2 openlane 1,113
3 fusesoc 1,079
4 edalize 574
5 pymtl3 333
6 hdl_checker 178
7 vcdvcd 49
8 sphinxcontrib-hdl-diagrams 48
9 cocotb-bus 44
10 PyChip-py-hcl 35
11 deepsocflow 32
12 teroshdl-documenter-demo 10
13 eda-log-file-warning-suppressor 1
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