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Top 23 Python Fpga Projects
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Project mention: Issue with Adafruit ESP32-S3: COM port switching, etc. | reddit.com/r/esp32 | 2023-03-06
You might have better luck with PlatformIO than the Arduino IDE; it's better at automatically choosing the serial port, though I can't say I've used it under Windows.
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Sonar
Write Clean Python Code. Always.. Sonar helps you commit clean code every time. With over 225 unique rules to find Python bugs, code smells & vulnerabilities, Sonar finds the issues while you focus on the work.
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Project mention: Why are there only 3 languages for FPGA development? | reddit.com/r/FPGA | 2022-12-01
He probably meant Amaranth.
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Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Project mention: OpenPOWER Foundation Demoes the LibreBMC Power-Based Open-Source BMC | news.ycombinator.com | 2022-10-23
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nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
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InfluxDB
Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.
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Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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It really depends on the type of data you are using. There may (or may not) be some trade offs and sacrifices. There are frameworks which can basically translate your neural network information from a high level python code into equivalent HLS code which is optimized for low latency when inferred on FPGAs. Some frameworks which might be useful for you to explore are hls4ml and finn. These are some frameworks which can achieve low latency inference of neural networks on FPGAs using Xilinx Vitis HLS. These are what I found when I did a similar experiment but with much lower latency target (a few hundred ns) and a very simple MLP with 1D signal as input which was a year ago. Not sure if there are better alternatives available as of 2023. But conceptually all these work on the primary principle of having a supporting framework/methodology to first quantize the network and limit the precision of data to fixed point. The HLS then produced will also be a result of the framework applying dataflow techniques such that the resulting HLS code will produce an RTL which has the best overall latency.
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I would check out hls4ml. It's an open source project made by/for people at CERN to convert neural networks created in Python using QKeras (a quantization extension of Keras) into HLS, with Vivado HLS being the most well supported. There are some caveats though, and a fellow student and I have had trouble getting the generated HLS to match the Keras model and be feasible to synthesize, but it seems to work well for smaller neural networks.
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PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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I had this recommended to me, but have yet to try it out: https://github.com/spcl/dace
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Also I would recommend SystemRDL for creating a definition usable in code generators: https://github.com/SystemRDL/systemrdl-compiler
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fxpmath
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
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Here is a python tool to modify netlist / edit files. https://github.com/byuccl/spydrnet
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sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
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NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
The latest post mention was on 2023-03-06.
Python Fpga related posts
- Dropping EDA-GUI's 101
- Introduction to FPGAs
- FPGA high-level programming
- Minix
- Using FPGAs for computations as a beginner
- Why are there only 3 languages for FPGA development?
- Generating pipeline stages automatically?
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Index
What are some of the best open-source Fpga projects in Python? This list will help you:
| Project | Stars | |
|---|---|---|
| 1 | PlatformIO | 6,673 |
| 2 | glasgow | 1,630 |
| 3 | amaranth | 1,098 |
| 4 | fusesoc | 940 |
| 5 | luna | 774 |
| 6 | prjxray | 639 |
| 7 | nmigen | 612 |
| 8 | edalize | 500 |
| 9 | finn | 487 |
| 10 | qkeras | 449 |
| 11 | PipelineC | 426 |
| 12 | dace | 353 |
| 13 | hBPF | 340 |
| 14 | systemrdl-compiler | 178 |
| 15 | pygears | 129 |
| 16 | fxpmath | 129 |
| 17 | spydrnet | 55 |
| 18 | sphinxcontrib-hdl-diagrams | 37 |
| 19 | PeakRDL-uvm | 36 |
| 20 | amalthea | 34 |
| 21 | conifer | 28 |
| 22 | PeakRDL-ipxact | 25 |
| 23 | sphinx-vhdl | 18 |
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