The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning. Learn more →
Top 23 Python Fpga Projects
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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Project mention: fusesoc VS vextproj - a user suggested alternative | libhunt.com/r/fusesoc | 2024-03-28
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Project mention: AMD Proposes an FPGA Subsystem User-Space Interface for Linux | news.ycombinator.com | 2024-01-04
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Project mention: Hi, What could be the best HLS tool for implementing neural networks on FPGA | /r/FPGA | 2023-06-13
FINN - https://github.com/Xilinx/finn
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nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Project mention: PipelineC Example: FM Radio Demodulation (FPGA SDR) | news.ycombinator.com | 2024-03-03Related: PipelineC: A C-like hardware description language (HDL):
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Project mention: Looking for HLS frameworks to start deploying DL algorithms on FPGAs | /r/FPGA | 2023-06-20
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fxpmath
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
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Project mention: AXOrderBook: NEW Extended Research - star count:53.0 | /r/algoprojects | 2023-10-22
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sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
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Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
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SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
Python Fpga related posts
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
- PipelineC Example: FM Radio Demodulation (FPGA SDR)
- AMD Proposes an FPGA Subsystem User-Space Interface for Linux
- Generate non-CPU FPGA circuits from a C-like language
- Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
- AXOrderBook: NEW Extended Research - star count:53.0
- AXOrderBook: NEW Extended Research - star count:53.0
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A note from our sponsor - WorkOS
workos.com | 29 Mar 2024
Index
What are some of the best open-source Fpga projects in Python? This list will help you:
Project | Stars | |
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1 | glasgow | 1,810 |
2 | amaranth | 1,411 |
3 | fusesoc | 1,103 |
4 | luna | 886 |
5 | prjxray | 728 |
6 | finn | 641 |
7 | nmigen | 635 |
8 | edalize | 579 |
9 | PipelineC | 534 |
10 | qkeras | 516 |
11 | dace | 456 |
12 | hBPF | 378 |
13 | icicle | 284 |
14 | systemrdl-compiler | 220 |
15 | fxpmath | 168 |
16 | pygears | 142 |
17 | spydrnet | 78 |
18 | AXOrderBook | 77 |
19 | sphinxcontrib-hdl-diagrams | 48 |
20 | PeakRDL-uvm | 45 |
21 | conifer | 40 |
22 | amalthea | 40 |
23 | naja | 38 |