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Top 23 Python Fpga Projects
A professional collaborative platform for embedded development :alien:Project mention: Issue with Adafruit ESP32-S3: COM port switching, etc. | reddit.com/r/esp32 | 2023-03-06
You might have better luck with PlatformIO than the Arduino IDE; it's better at automatically choosing the serial port, though I can't say I've used it under Windows.
Scots Army Knife for electronics
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A modern hardware definition language and toolchain based on PythonProject mention: Why are there only 3 languages for FPGA development? | reddit.com/r/FPGA | 2022-12-01
He probably meant Amaranth.
Package manager and build abstraction tool for FPGA/ASIC developmentProject mention: Introduction to FPGAs | news.ycombinator.com | 2023-02-06
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
a USB multitool + Amaranth HDL framework for monitoring, hacking, and developing USB devices
Documenting the Xilinx 7-series bit-stream format.Project mention: OpenPOWER Foundation Demoes the LibreBMC Power-Based Open-Source BMC | news.ycombinator.com | 2022-10-23
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
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An abstraction library for interfacing EDA toolsProject mention: Dropping EDA-GUI's 101 | reddit.com/r/FPGA | 2023-02-17
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
Dataflow compiler for QNN inference on FPGAsProject mention: Sub ms - 3ms Latency Vision task on FPGA | reddit.com/r/FPGA | 2023-02-05
It really depends on the type of data you are using. There may (or may not) be some trade offs and sacrifices. There are frameworks which can basically translate your neural network information from a high level python code into equivalent HLS code which is optimized for low latency when inferred on FPGAs. Some frameworks which might be useful for you to explore are hls4ml and finn. These are some frameworks which can achieve low latency inference of neural networks on FPGAs using Xilinx Vitis HLS. These are what I found when I did a similar experiment but with much lower latency target (a few hundred ns) and a very simple MLP with 1D signal as input which was a year ago. Not sure if there are better alternatives available as of 2023. But conceptually all these work on the primary principle of having a supporting framework/methodology to first quantize the network and limit the precision of data to fixed point. The HLS then produced will also be a result of the framework applying dataflow techniques such that the resulting HLS code will produce an RTL which has the best overall latency.
QKeras: a quantization deep learning library for Tensorflow KerasProject mention: How to build FPGA-based ML accelerator? | reddit.com/r/FPGA | 2022-07-06
I would check out hls4ml. It's an open source project made by/for people at CERN to convert neural networks created in Python using QKeras (a quantization extension of Keras) into HLS, with Vivado HLS being the most well supported. There are some caveats though, and a fellow student and I have had trouble getting the generated HLS to match the Keras model and be feasible to synthesize, but it seems to work well for smaller neural networks.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.Project mention: Using FPGAs for computations as a beginner | reddit.com/r/FPGA | 2022-12-23
DaCe - Data Centric Parallel ProgrammingProject mention: FPGA high-level programming | reddit.com/r/FPGA | 2023-02-02
I had this recommended to me, but have yet to try it out: https://github.com/spcl/dace
hBPF = eBPF in hardwareProject mention: HBPF – eBPF in Hardware | reddit.com/r/hardware | 2022-04-01
SystemRDL 2.0 language compiler front-endProject mention: Tool to generate table of memory-mapped register? | reddit.com/r/FPGA | 2023-02-11
Also I would recommend SystemRDL for creating a definition usable in code generators: https://github.com/SystemRDL/systemrdl-compiler
HW Design: A Functional Approach
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.Project mention: Variable sized signed integer arithmetic library | reddit.com/r/FPGA | 2022-10-06
A flexible framework for analyzing and transforming FPGA netlists. Official repository.Project mention: Is there a minimal HDL? | reddit.com/r/FPGA | 2022-06-02
Here is a python tool to modify netlist / edit files. https://github.com/byuccl/spydrnet
Sphinx Extension which generates various types of diagrams from Verilog code.
Generate UVM register model from compiled SystemRDL input
an experimental SDR platform
Fast inference of Boosted Decision Trees in FPGAs (by thesps)
Import and export IP-XACT XML register models
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Python Fpga related posts
Dropping EDA-GUI's 101
1 project | reddit.com/r/FPGA | 17 Feb 2023
Introduction to FPGAs
9 projects | news.ycombinator.com | 6 Feb 2023
FPGA high-level programming
1 project | reddit.com/r/FPGA | 2 Feb 2023
2 projects | reddit.com/r/linuxmemes | 13 Jan 2023
Using FPGAs for computations as a beginner
3 projects | reddit.com/r/FPGA | 23 Dec 2022
Why are there only 3 languages for FPGA development?
5 projects | reddit.com/r/FPGA | 1 Dec 2022
Generating pipeline stages automatically?
2 projects | reddit.com/r/FPGA | 27 Nov 2022
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What are some of the best open-source Fpga projects in Python? This list will help you: