Top 6 Python Systemverilog Projects

edalize

4 590 7.3 Python

An abstraction library for interfacing EDA tools
pymtl3

5 348 5.2 Python

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Project mention: Firrtl – Flexible Intermediate Representation for RTL | news.ycombinator.com | 2023-07-15

InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
hdl_checker

4 182 0.0 Python

Repurposing existing HDL tools to help writing better code
deepsocflow

1 34 9.2 Python

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
fsm2sv

1 20 2.4 Python

SystemVerilog FSM generator
teroshdl-documenter-demo

1 10 0.0 Python

This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).