Python Vhdl

Open-source Python projects categorized as Vhdl
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Topics: Verilog Python Fpga Systemverilog Xilinx
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Top 14 Python Vhdl Projects

  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    • Project mention: Designing a Low Latency 10G Ethernet Core | /r/FPGA | 2023-07-04

    The use of cocotb and pyuvm for verification

  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    • Project mention: fusesoc VS vextproj - a user suggested alternative | libhunt.com/r/fusesoc | 2024-03-28

  • WorkOS

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  • edalize

    An abstraction library for interfacing EDA tools

  • PipelineC

    A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

    • Project mention: PipelineC Example: FM Radio Demodulation (FPGA SDR) | news.ycombinator.com | 2024-03-03

    Related: PipelineC: A C-like hardware description language (HDL):

    https://github.com/JulianKemmerer/PipelineC

  • hdl_checker

    Repurposing existing HDL tools to help writing better code

  • vhdl-style-guide

    Style guide enforcement for VHDL

  • cocotb-bus

    Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • VHDLproc

    VHDLproc is a VHDL preprocessor

  • neorv32-riscof

    ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

  • sphinx-vhdl

  • FPGA_HW_SIM_FWK_2

    FPGA Hardware Simulation Framework

    • Project mention: Simulating FPGA without having to buy the boards? | /r/FPGA | 2023-06-24

    Here's what looks to be an extension of that project - looks quite interesting, throws in circuit.js aswell https://github.com/ClarkFieseln/FPGA_HW_SIM_FWK_2

  • logidiff

    A website and Python library for determining if two logical statements are equivalent. Uses VHDL syntax and logical operators.

  • teroshdl-documenter-demo

    This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

  • eda-log-file-warning-suppressor

    Suppresses warnings in EDA logfiles.

  • SaaSHub

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Python Vhdl related posts

Index

What are some of the best open-source Vhdl projects in Python? This list will help you:

Project Stars
1 cocotb 1,599
2 fusesoc 1,115
3 edalize 590
4 PipelineC 541
5 hdl_checker 182
6 vhdl-style-guide 169
7 cocotb-bus 46
8 VHDLproc 24
9 neorv32-riscof 24
10 sphinx-vhdl 19
11 FPGA_HW_SIM_FWK_2 16
12 logidiff 11
13 teroshdl-documenter-demo 10
14 eda-log-file-warning-suppressor 2

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