neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (by stnolting)
riscv
RISC-V CPU Core (RV32IM) (by ultraembedded)
| neorv32-verilog | riscv | |
|---|---|---|
| 5 | 2 | |
| 40 | 1,040 | |
| - | - | |
| 8.1 | 1.8 | |
| 6 days ago | over 2 years ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32-verilog
Posts with mentions or reviews of neorv32-verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-10.
-
Converting VHDL to Verilog using GHDL
I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog
- Convert VHDL to Verilog using GHDL (using a RISC-V core as example)
- Show HN: Convert VHDL to Verilog using GHDL (+ first evaluation)
riscv
Posts with mentions or reviews of riscv.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
What are some alternatives?
When comparing neorv32-verilog and riscv you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
serv - SERV - The SErial RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
ghdl - VHDL 2008/93/87 simulator
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
naja - Structural Netlist API (and more) for EDA post synthesis flow development
zipcpu - A small, light weight, RISC CPU soft core
edalize - An abstraction library for interfacing EDA tools
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
uhd - The USRP™ Hardware Driver Repository
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs