Verilog pipeline-processor

Open-source Verilog projects categorized as pipeline-processor
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Topics: risc-v Asic Fpga Verilog Verification
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Verilog pipeline-processor Projects

  • riscv

    RISC-V CPU Core (RV32IM)

    Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

    I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-04.

Index

Project Stars
1 riscv 1,040

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