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Top 6 Verilog Rv32i Projects
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
Project mention: Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS | /r/FPGA | 2023-06-03The project repository and the details about the paper can be found here.
Project mention: SoC RISC-V: An ASIC Implementation of the FEMTORV32 | news.ycombinator.com | 2023-12-20
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Verilog Rv32i related posts
- Need help with designing a basic RISC V processor?
- Не слабо так у турков бомбануло после сожжения Корана у посольства Турции в Стокгольме
- As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
- BiRISC-V – 32-bit Superscalar RISC-V CPU
- Need help learning how to use risc-v toolchain
- [github] biRISC-V - 32-bit dual issue RISC-V CPU
- [github] biRISC-V - 32-bit dual issue RISC-V CPU
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A note from our sponsor - InfluxDB
www.influxdata.com | 25 Apr 2024
Index
What are some of the best open-source Rv32i projects in Verilog? This list will help you:
Project | Stars | |
---|---|---|
1 | darkriscv | 1,882 |
2 | riscv | 1,040 |
3 | biriscv | 749 |
4 | RISC-V | 42 |
5 | ITA-CORES | 33 |
6 | fpga_riscv_cpu | 8 |
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