Top 7 Verilog Cpu Projects

darkriscv

3 1,873 6.8 Verilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zipcpu

13 1,188 6.3 Verilog

A small, light weight, RISC CPU soft core
InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
riscv

2 1,040 1.8 Verilog

RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

biriscv

6 749 0.0 Verilog

32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

riscv_vhdl

2 578 8.8 Verilog

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
spam-1

1 60 4.0 Verilog

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
RISC-V

1 41 7.6 Verilog

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Project mention: Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS | /r/FPGA | 2023-06-03

The project repository and the details about the paper can be found here.

WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-04.