Top 7 Verilog Cpu Projects

darkriscv

0 1,727 0.0 Verilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zipcpu

1 1,099 4.1 Verilog

A small, light weight, RISC CPU soft core

Project mention: Xilinx FIFO generator for skid buffer? | /r/FPGA | 2022-10-20

For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
SonarLint

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riscv

1 902 1.8 Verilog

RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
biriscv

2 644 0.0 Verilog

32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21
riscv_vhdl

0 535 0.0 Verilog

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
spam-1

0 53 0.0 Verilog

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
RISC-V

1 22 10.0 Verilog

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Project mention: Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS | /r/FPGA | 2023-06-03

The project repository and the details about the paper can be found here.
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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-04.