Verilog risc-v

Open-source Verilog projects categorized as risc-v Edit details
Related topics: #Asic #Fpga #Verilog #Cpu #Rv32i

Top 3 Verilog risc-v Projects

  • serv

    SERV - The SErial RISC-V CPU

    Project mention: RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021 | news.ycombinator.com | 2022-06-21

    The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.

    https://github.com/olofk/serv#good-to-know

  • riscv

    RISC-V CPU Core (RV32IM) (by ultraembedded)

    Project mention: I made my own silicon chip: Project Silicon Rider | news.ycombinator.com | 2021-10-03
  • SonarQube

    Static code analysis for 29 languages.. Your projects are multi-language. So is SonarQube analysis. Find Bugs, Vulnerabilities, Security Hotspots, and Code Smells so you can release quality code every time. Get started analyzing your projects today for free.

  • biriscv

    32-bit Superscalar RISC-V CPU

    Project mention: BiRISC-V – 32-bit Superscalar RISC-V CPU | news.ycombinator.com | 2021-07-20
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2022-06-21.

Verilog risc-v related posts

Index

What are some of the best open-source risc-v projects in Verilog? This list will help you:

Project Stars
1 serv 768
2 riscv 550
3 biriscv 409
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