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Top 8 Verilog risc-v Projects
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I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
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airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
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Project mention: Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS | /r/FPGA | 2023-06-03
The project repository and the details about the paper can be found here.
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Verilog risc-v related posts
- Ultraembedded RISCV Module
- SERV: A bit-serial RISC-V core
- Need help with designing a basic RISC V processor?
- SERV – open-source Tiny SErial RISC-V CPU
- How to build a Startup use open source chips
- How many gates does a decent risc-v implementation take?
- Open-source RISC-V CPU projects for contribution
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Index
What are some of the best open-source risc-v projects in Verilog? This list will help you:
Project | Stars | |
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1 | darkriscv | 1,727 |
2 | serv | 1,087 |
3 | riscv | 902 |
4 | biriscv | 644 |
5 | Hazard3 | 62 |
6 | airisc_core_complex | 60 |
7 | RISC-V | 22 |
8 | fpga_riscv_cpu | 7 |