neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (by stnolting)
biriscv
32-bit Superscalar RISC-V CPU (by ultraembedded)
| neorv32-verilog | biriscv | |
|---|---|---|
| 5 | 6 | |
| 40 | 749 | |
| - | - | |
| 8.1 | 0.0 | |
| 5 days ago | over 2 years ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32-verilog
Posts with mentions or reviews of neorv32-verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-10.
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Converting VHDL to Verilog using GHDL
I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog
- Convert VHDL to Verilog using GHDL (using a RISC-V core as example)
- Show HN: Convert VHDL to Verilog using GHDL (+ first evaluation)
biriscv
Posts with mentions or reviews of biriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-21.
What are some alternatives?
When comparing neorv32-verilog and biriscv you can also consider the following projects:
riscv - RISC-V CPU Core (RV32IM)
serv - SERV - The SErial RISC-V CPU
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
ghdl - VHDL 2008/93/87 simulator
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
naja - Structural Netlist API (and more) for EDA post synthesis flow development
zipcpu - A small, light weight, RISC CPU soft core
edalize - An abstraction library for interfacing EDA tools
vgasim - A Video display simulator
wbicapetwo - Wishbone to ICAPE interface conversion
RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension