biriscv VS sdspi

Compare biriscv vs sdspi and see what are their differences.

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biriscv sdspi
6 4
749 132
- -
0.0 7.5
over 2 years ago about 1 month ago
Verilog Verilog
Apache License 2.0 -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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biriscv

Posts with mentions or reviews of biriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-21.

sdspi

Posts with mentions or reviews of sdspi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-11.
  • C++ Verification Testbench Best-Practice Resources?
    7 projects | /r/FPGA | 11 Jun 2023
    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
  • Envisioning the Ultimate I2C Controller
    1 project | /r/ZipCPU | 18 Nov 2021
    You mean ... sort of like I did in this project? I implemented an SPI based controller, where the controller took care of all the bit-banging for you, but the CPU still needed to issue the commands as appropriate for the protocol?
  • SoC FPGA design to ASIC
    4 projects | /r/FPGA | 22 Jul 2021
    How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.
  • CPU DESIGN
    9 projects | /r/FPGA | 5 Apr 2021
    There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.

What are some alternatives?

When comparing biriscv and sdspi you can also consider the following projects:

riscv - RISC-V CPU Core (RV32IM)

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

dpll - A collection of phase locked loop (PLL) related projects

zipcpu - A small, light weight, RISC CPU soft core

wb2axip - Bus bridges and other odds and ends

vgasim - A Video display simulator

Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL

wbicapetwo - Wishbone to ICAPE interface conversion

nybbleForth - Stack machine with 4-bit instructions

RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

videozip - A ZipCPU SoC for the Nexys Video board supporting video functionality