Verilog Xilinx

Open-source Verilog projects categorized as Xilinx

Top 3 Verilog Xilinx Projects

  • biriscv

    32-bit Superscalar RISC-V CPU

    Project mention: Не слабо так у турков бомбануло после сожжения Корана у посольства Турции в Стокгольме | reddit.com/r/tjournal_refugees | 2023-01-24
  • wb2axip

    Bus bridges and other odds and ends

    Project mention: Simple skid buffer implementation | reddit.com/r/FPGA | 2023-01-10

    I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)

  • InfluxDB

    Build time-series-based applications quickly and at scale.. InfluxDB is the Time Series Platform where developers build real-time applications for analytics, IoT and cloud-native services. Easy to start, it is available in the cloud or on-premises.

  • wbicapetwo

    Wishbone to ICAPE interface conversion

    Project mention: Can an FPGA program itself? | reddit.com/r/FPGA | 2022-07-21
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-01-24.

Verilog Xilinx related posts

Index

What are some of the best open-source Xilinx projects in Verilog? This list will help you:

Project Stars
1 biriscv 505
2 wb2axip 330
3 wbicapetwo 5
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