Verilog wishbone

Open-source Verilog projects categorized as wishbone

Top 9 Verilog wishbone Projects

  • zipcpu

    A small, light weight, RISC CPU soft core

  • wb2axip

    Bus bridges and other odds and ends

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

    WorkOS logo
  • wbuart32

    A simple, basic, formally verified UART controller

  • Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

  • sdspi

    SD-Card controller, using either SPI, SDIO, or eMMC interfaces

  • Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

  • openarty

    An Open Source configuration of the Arty platform

  • Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

  • wbscope

    A wishbone controlled scope for FPGA's

  • dbgbus

    A collection of debugging busses developed and presented at zipcpu.com

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo
  • wbfmtx

    A wishbone controlled FM transmitter hack

  • wbicapetwo

    Wishbone to ICAPE interface conversion

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Verilog wishbone related posts

Index

What are some of the best open-source wishbone projects in Verilog? This list will help you:

Project Stars
1 zipcpu 1,190
2 wb2axip 431
3 wbuart32 250
4 sdspi 132
5 openarty 116
6 wbscope 70
7 dbgbus 31
8 wbfmtx 19
9 wbicapetwo 8

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