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Top 8 Verilog wishbone Projects
A small, light weight, RISC CPU soft coreProject mention: Xilinx FIFO generator for skid buffer? | reddit.com/r/FPGA | 2022-10-20
For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
Bus bridges and other odds and endsProject mention: Simple skid buffer implementation | reddit.com/r/FPGA | 2023-01-10
I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)
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A simple, basic, formally verified UART controllerProject mention: CDC interview question clarification | reddit.com/r/FPGA | 2022-05-22
Try this one.
An Open Source configuration of the Arty platformProject mention: PPS detection/regeneration | reddit.com/r/FPGA | 2022-05-25
The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
SD-Card controller, using a SPI interface that is (optionally) shared
A wishbone controlled scope for FPGA's
A collection of debugging busses developed and presented at zipcpu.com
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Wishbone to ICAPE interface conversionProject mention: Can an FPGA program itself? | reddit.com/r/FPGA | 2022-07-21
Verilog wishbone related posts
Simple skid buffer implementation
3 projects | reddit.com/r/FPGA | 10 Jan 2023
Testing Axi Slaves in Simulation
1 project | reddit.com/r/FPGA | 4 Jan 2023
Looking to implimenting an autocorrelation function (ACF) into one of my projects.
3 projects | reddit.com/r/FPGA | 24 Nov 2022
Guys can u send me some github repositories on some simple project on system verilog with functionality like with couple functions ? Its my first reddit post in my life.
1 project | reddit.com/r/FPGA | 14 Nov 2022
A simple AXI-Lite register file
1 project | reddit.com/r/FPGA | 24 Oct 2022
AXI-Lite register bank revisited
1 project | reddit.com/r/FPGA | 22 Oct 2022
Xilinx FIFO generator for skid buffer?
2 projects | reddit.com/r/FPGA | 20 Oct 2022
A note from our sponsor - SonarLint
www.sonarlint.org | 28 Mar 2023
What are some of the best open-source wishbone projects in Verilog? This list will help you: