Verilog wishbone

Open-source Verilog projects categorized as wishbone

Top 8 Verilog wishbone Projects

  • zipcpu

    A small, light weight, RISC CPU soft core

    Project mention: Xilinx FIFO generator for skid buffer? | | 2022-10-20

    For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.

  • wb2axip

    Bus bridges and other odds and ends

    Project mention: Simple skid buffer implementation | | 2023-01-10

    I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)

  • SonarLint

    Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.

  • wbuart32

    A simple, basic, formally verified UART controller

    Project mention: CDC interview question clarification | | 2022-05-22

    Try this one.

  • openarty

    An Open Source configuration of the Arty platform

    Project mention: PPS detection/regeneration | | 2022-05-25

    The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.

  • sdspi

    SD-Card controller, using a SPI interface that is (optionally) shared

  • wbscope

    A wishbone controlled scope for FPGA's

  • dbgbus

    A collection of debugging busses developed and presented at

  • InfluxDB

    Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.

  • wbicapetwo

    Wishbone to ICAPE interface conversion

    Project mention: Can an FPGA program itself? | | 2022-07-21
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-01-10.

Verilog wishbone related posts


What are some of the best open-source wishbone projects in Verilog? This list will help you:

Project Stars
1 zipcpu 1,008
2 wb2axip 339
3 wbuart32 200
4 openarty 104
5 sdspi 76
6 wbscope 61
7 dbgbus 23
8 wbicapetwo 5
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