Top 8 Verilog wishbone Projects

zipcpu

2 1,008 5.7 Verilog

A small, light weight, RISC CPU soft core

Project mention: Xilinx FIFO generator for skid buffer? | reddit.com/r/FPGA | 2022-10-20

For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
wb2axip

13 339 4.9 Verilog

Bus bridges and other odds and ends

Project mention: Simple skid buffer implementation | reddit.com/r/FPGA | 2023-01-10

I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)
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wbuart32

1 200 0.0 Verilog

A simple, basic, formally verified UART controller

Project mention: CDC interview question clarification | reddit.com/r/FPGA | 2022-05-22

Try this one.
openarty

2 104 2.5 Verilog

An Open Source configuration of the Arty platform

Project mention: PPS detection/regeneration | reddit.com/r/FPGA | 2022-05-25

The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
sdspi

0 76 0.0 Verilog

SD-Card controller, using a SPI interface that is (optionally) shared
wbscope

0 61 0.8 Verilog

A wishbone controlled scope for FPGA's
dbgbus

0 23 0.0 Verilog

A collection of debugging busses developed and presented at zipcpu.com
InfluxDB

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wbicapetwo

1 5 0.0 Verilog

Wishbone to ICAPE interface conversion

Project mention: Can an FPGA program itself? | reddit.com/r/FPGA | 2022-07-21

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-01-10.