Top 13 Verilog Verilator Projects

zipcpu

3 1,006 5.6 Verilog

A small, light weight, RISC CPU soft core

Project mention: Xilinx FIFO generator for skid buffer? | reddit.com/r/FPGA | 2022-10-20

For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
riscv

0 742 1.0 Verilog

RISC-V CPU Core (RV32IM) (by ultraembedded)
InfluxDB

www.influxdata.com
sponsored

Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.
biriscv

1 544 0.0 Verilog

32-bit Superscalar RISC-V CPU

Project mention: Не слабо так у турков бомбануло после сожжения Корана у посольства Турции в Стокгольме | reddit.com/r/tjournal_refugees | 2023-01-24
wbuart32

1 200 0.0 Verilog

A simple, basic, formally verified UART controller

Project mention: CDC interview question clarification | reddit.com/r/FPGA | 2022-05-22

Try this one.
vgasim

1 121 0.0 Verilog

A Video display simulator

Project mention: Sobel algorithm in VHDL help | reddit.com/r/FPGA | 2022-05-17

Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.
openarty

2 104 2.5 Verilog

An Open Source configuration of the Arty platform

Project mention: PPS detection/regeneration | reddit.com/r/FPGA | 2022-05-25

The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
sdspi

0 76 0.0 Verilog

SD-Card controller, using a SPI interface that is (optionally) shared
SonarLint

www.sonarlint.org
sponsored

Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.
dpll

1 68 0.0 Verilog

A collection of phase locked loop (PLL) related projects

Project mention: PLL simulation in Vivado | reddit.com/r/FPGA | 2022-08-10

For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.
wbscope

0 61 0.8 Verilog

A wishbone controlled scope for FPGA's
zbasic

0 36 0.0 Verilog

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
interpolation

0 32 0.8 Verilog

Digital Interpolation Techniques Applied to Digital Signal Processing
dbgbus

0 23 0.0 Verilog

A collection of debugging busses developed and presented at zipcpu.com
wbicapetwo

1 5 0.0 Verilog

Wishbone to ICAPE interface conversion

Project mention: Can an FPGA program itself? | reddit.com/r/FPGA | 2022-07-21

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-01-24.