Top 13 Verilog Verilator Projects

zipcpu

0 1,188 6.3 Verilog

A small, light weight, RISC CPU soft core
riscv

1 1,040 1.8 Verilog

RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
WorkOS

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biriscv

1 749 0.0 Verilog

32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21
wbuart32

1 246 4.6 Verilog

A simple, basic, formally verified UART controller

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
vgasim

1 147 1.2 Verilog

A Video display simulator

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
sdspi

1 132 7.5 Verilog

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
openarty

1 116 0.0 Verilog

An Open Source configuration of the Arty platform

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
InfluxDB

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dpll

0 87 2.8 Verilog

A collection of phase locked loop (PLL) related projects
wbscope

0 70 3.7 Verilog

A wishbone controlled scope for FPGA's
interpolation

0 46 3.2 Verilog

Digital Interpolation Techniques Applied to Digital Signal Processing
zbasic

0 39 0.0 Verilog

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
dbgbus

0 31 3.9 Verilog

A collection of debugging busses developed and presented at zipcpu.com
wbicapetwo

0 8 0.0 Verilog

Wishbone to ICAPE interface conversion

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-04.