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Top 13 Verilog Verilator Projects
A small, light weight, RISC CPU soft coreProject mention: Xilinx FIFO generator for skid buffer? | reddit.com/r/FPGA | 2022-10-20
For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
RISC-V CPU Core (RV32IM) (by ultraembedded)
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32-bit Superscalar RISC-V CPUProject mention: Не слабо так у турков бомбануло после сожжения Корана у посольства Турции в Стокгольме | reddit.com/r/tjournal_refugees | 2023-01-24
A simple, basic, formally verified UART controllerProject mention: CDC interview question clarification | reddit.com/r/FPGA | 2022-05-22
Try this one.
A Video display simulatorProject mention: Sobel algorithm in VHDL help | reddit.com/r/FPGA | 2022-05-17
Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.
An Open Source configuration of the Arty platformProject mention: PPS detection/regeneration | reddit.com/r/FPGA | 2022-05-25
The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
SD-Card controller, using a SPI interface that is (optionally) shared
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A collection of phase locked loop (PLL) related projectsProject mention: PLL simulation in Vivado | reddit.com/r/FPGA | 2022-08-10
For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.
A wishbone controlled scope for FPGA's
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Digital Interpolation Techniques Applied to Digital Signal Processing
A collection of debugging busses developed and presented at zipcpu.com
Wishbone to ICAPE interface conversionProject mention: Can an FPGA program itself? | reddit.com/r/FPGA | 2022-07-21
Verilog Verilator related posts
Five legally free FPGA books (plus one about Machine Learning)
1 project | reddit.com/r/FPGA | 6 Sep 2022
PLL simulation in Vivado
1 project | reddit.com/r/FPGA | 10 Aug 2022
Can an FPGA program itself?
1 project | reddit.com/r/FPGA | 21 Jul 2022
2 projects | reddit.com/r/FPGA | 25 May 2022
CDC interview question clarification
1 project | reddit.com/r/FPGA | 22 May 2022
What make xilinx fpga runs soft core cpu faster than lattice
1 project | reddit.com/r/FPGA | 27 Mar 2022
AXI Quad SPI 3.2 Flash programming scripts
5 projects | reddit.com/r/FPGA | 10 Jan 2022
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What are some of the best open-source Verilator projects in Verilog? This list will help you: